TDA5230 Infineon Technologies, TDA5230 Datasheet - Page 76

• Manufacturer Part Number: TDA5230
• Description: IC RECEIVER ASK/FSK 28-TSSOP
• Manufacturer: Infineon Technologies
• Type: Receiverr

Specifications of TDA5230

• Package / Case: 28-TSSOP
• Frequency: 433MHz ~ 450MHz, 865MHz ~ 868MHz
• Sensitivity: -111dBm
• Data Rate - Maximum: 20 kbps
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, TPM, Security Systems
• Current - Receiving: 8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Operating Frequency: 870 MHz
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: SP000076520; TDA5230; TDA5230INTR

Peak Detector 2 is used to measure RSSI independent of a data transfer and to digitally
trim RSSI. It is read via SFR RSSI2.
Observation of the RSSI signal is active whenever the RX-RUN signal is high. The
RSSI2 register is refreshed and Peak Detector 2 is reset after every read access to
RSSI2.
It may be required to read RSSI2 twice to obtain the required result. This is because, for
example, during a trim procedure input signal power is reduced, after reading RSSI2, the
peak detector will still hold the higher RSSI level. After reading RSSI2 the lower RSSI
level is loaded into the Peak Detector, and can be read by reading RSSI2 again.
When the RX-RUN signal is inactive, a read access has no influence to the peak detector
value. The register RSSI2 is reset to 0 at power up reset.
Figure 35
The following figure shows the typical behavior of the digital RSSI. Three curves show
the typical trimming range, the typical default RSSI, and the fourth curve shows a
typically trimmed RSSI.
Data Sheet
RSSI1 & RSSI2
internal RSSI1
RSSI1 Register
internal RSSI
internal RSSI2 =
RSSI2 Register
internal RSSI
Data-Pattern
SPI read out
*1 Computation Delay due to filtering and signal calculation.
Input
Peak Detector Behavior
Noise
Reset
Run-In
FSYNC clears the
internal RSSI1
TSI
D0
D1
*1
FSync
....
Dn
-1
Dn
n = PKBITPOS
Dn
+1
*1
72
Dn
+2
Dn
+3
SPI
....
EOM
Functional Description
Noise
*1
Version 4.0, 2007-06-01
EOM
Run-In
TSI
D0 D1
TDA523x
*1
FSync
....