SI4735-B20-GM Silicon Laboratories Inc, SI4735-B20-GM Datasheet - Page 8

• Manufacturer Part Number: SI4735-B20-GM
• Description: IC RX AM/FM/SW/LW RAD RDS 20UQFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4735-B20-GM

• Package / Case: 20-UQFN, 20-µQFN
• Frequency: 153kHz ~ 279kHz, 520kHz ~ 1.71MHz, 2.3MHz ~ 21.85MHz, 64MHz ~ 108MHz
• Modulation Or Protocol: AM, FM, LW-SW, WB
• Applications: General Purpose
• Current - Receiving: 19.9mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: RSSI Equipped
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -20°C ~ 85°C
• Bus Type: I2C
• Maximum Frequency: 108 MHz, 1710 MHz
• Minimum Frequency: 76 MHz, 520 MHz
• Modulation Technique: AM, FM
• Mounting Style: SMD/SMT
• Function: Radio
• Supply Voltage (min): 2.7 V
• Supply Voltage (max): 5.5 V
• Minimum Operating Temperature: - 20 C
• Maximum Operating Temperature: + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Lead Free Status / Rohs Status: Compliant

Si473x-B20
Table 5. 2-Wire Control Interface Characteristics
(V
8
Parameter
SCLK Frequency
SCLK Low Time
SCLK High Time
SCLK Input to SDIO
(START)
SCLK Input to SDIO
(START)
SDIO Input to SCLK
SDIO Input to SCLK
SCLK input to SDIO
(STOP)
STOP to START Time
SDIO Output Fall Time
SDIO Input, SCLK Rise/Fall Time
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
DD
1. When V
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
4. The Si473x delays SDIO by a minimum of 300 ns from the V
5. The maximum t
= 2.7 to 5.5 V, V
high) does not occur within 300 ns before the rising edge of RST.
until after the first start condition.
specification.
violated as long as all other timing parameters are met.
IO
= 0 V, SCLK and SDIO are low impedance.
IO
HD:DAT





= 1.5 to 3.6 V, T
Setup
Setup
Hold
Setup
Hold
has only to be met when f
4,5
A
= –20 to 85 °C)
Symbol
t
t
t
t
t
HD:STA
SU:DAT
HD:DAT
SU:STO
SU:STA
t
t
t
f
t
f:OUT
HIGH
t
LOW
t
BUF
t
SCL
C
f:IN
r:IN
SP
b
SCL
Test Condition
Rev. 0.5
= 400 kHz. At frequencies below 400 KHz, t
1,2,3
IH
threshold of SCLK to comply with the minimum t
20
20
+
+
Min
100
1.3
0.6
0.6
0.6
0.6
1.3
0.1
0.1
—
—
0
0
---------- -
1pF
---------- -
1pF
C
C
b
b
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
HD:DAT
Max
400
900
250
300
50
50
—
—
—
—
—
—
—
may be
HD:DAT
Unit
kHz
pF
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns