TDA7528 STMicroelectronics, TDA7528 Datasheet - Page 41

• Manufacturer Part Number: TDA7528
• Description: IC FRONT END MODULE CAR 64-LQFP
• Manufacturer: STMicroelectronics

Specifications of TDA7528

• Frequency: 50kHz ~ 108MHz, 161MHz ~ 163MHz
• Modulation Or Protocol: AM, FM
• Applications: Automotive Audio
• Current - Receiving: 175mA
• Data Interface: PCB, Surface Mount
• Voltage - Supply: 3.3V, 5V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 125C
• Operating Temperature Classification: Automotive
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Antenna Connector: -
• Lead Free Status / Rohs Status: Compliant

TDA7528
5
5.1
Note:
Programming information
Address organization
Figure 9.
The power on value of all registers is zero.
Name
Short reg
ADCctrl
GPIOmode
AGCmixCtrl
Supply
DivR1
IFAGC
FMAGC
FM_AM_Vthr
MIXalign1
MIXalign2
PLLctrl
PLLctrl2
PLLtest
Misc1
Misc2
AGCtc_A
AMAGC_A
GPIOm_A
IFCTRL_A
DivV_A
DivN_A1
DivN_A2
DivN_A3
DivR2_A
CPcur_A
DAC1_A
DAC2_A
PLL_DAC_A
AMFilt_A
Misc3_A
ADCtest_A
AGCtc_B
AMAGC_B
GPIOm_B
IFCTRL_B
DivV_B
DivN_B1
DivN_B2
DivN_B3
DivR2_B
CPcur_B
DAC1_B
DAC2_B
PLL_DAC_B
AMFilt_B
Misc3_B
ADCtest_B
READ_Status
READ_ADC
No r/w
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
0
1
2
3
4
5
6
7
8
9
49
Address organization
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r
r
initialization registers, to be changed after power on
depends on reception band (FM / MW / SW / …)
to be changed with each frequency change
additional controls, changed indipendent from reception
IF buffer control
test registers, not to be changed at all
IFin0_Std_IBOC
IFAGC_FM_AM
CompDAC3
IFAGCtcAM
AMAGCfat
refmode1
AGCtest1
DAC1A8
DAC2A8
AMfiltA7
IMRph3
IFbufG2
GPO8hl
divnA20
divnA12
ADCclk
FMthr3
AMthr3
VCO1r
divnA4
CPAh3
IQselA
AAfilt1
GPO8
divr15
IF test
MSB
divr7
DZ2
POL
x
all bytes from 33 to 47 are valid on the output if SHPLL is set to '1', otherwise byte 17 to 31 are valid on the output
PWRSTABLEw
AM2nd_order
IFAmpgainA2
CompDAC2
IFAGCtcFM
KeyAGCen
IFAGCthr2
refmode0
AGCtest0
DAC1A7
DAC2A7
ADC test
PFD_D1
divnA19
divnA11
AMfiltA6
IMRph2
IFbufG1
GPO7hl
VCOsw
ADCs2
FMthr2
AMthr2
divVA6
divnA3
CPAh2
ADCok
AAfilt0
GPO7
divr14
divr6
DZ1
6
this byte is valid on the output if bit SHAGC is set to '1', otherwise byte Nr. 16 is valid on the output
Doc ID 13141 Rev 6
IFAmpgainA1
BalunoutIMP
FMAGCpwr
CompDAC1
IFAGCthr1
ADCDAC5
PFD_D0
GPIO6hl
DAC1A6
DAC2A6
AMfiltA5
IMRph1
IFbufG0
divnA18
divnA10
ShAGC
DivRen
CPctrl1
GPIO6r
ADCs1
FMthr1
AMthr1
divVA6
CPAh1
GPIO6
divnA2
divr13
AMtc1
ADC5
Vthr5
divr5
DS2
5
VCCmon_adj1
IFAmpgainA0
AMAGCpwr
CompDAC0
IFAGCthr0
Ired_Balun
ADCDAC4
GPIO5hl
DAC1A5
DAC2A5
divnA17
AMfiltA4
IMRph0
GPIO5r
ADCs0
FMthr0
AMthr0
divVA6
CPctrl0
ShPLL
GPIO5
PLLT4
IFbufin
divnA9
divnA1
divr12
AMtc0
CPAl4
ADC4
Vthr4
divr4
DS1
4
FMAGCmodeC1
AMAGCmodeC1
CompDACtest2
VCCmon_adj0
PWR_stable
ADCDAC3
IFbufPWR
ADCstart
MixinFM
DAC1A4
DAC2A4
DAC2A0
DIVVtest
GPO4hl
divnA16
AMfiltA3
Mix_ctrl
VCOext
IMRG3
divVA6
PLLT3
divnA8
divnA0
GPO4
divr11
FMtc3
CPAl3
ADC3
IredH
Vthr3
divr3
3
AMAGCmodeC0
FMAGCmodeC0
CompDACtest1
MixinAM_LPF
En_VCCmon
ADCDAC2
RCenable
MaskSet0
PLLtest2
DAC1A3
DAC2A3
RC_test
divnA15
AmfiltA2
divnA21
GPO3hl
ADCen
IMRG2
divVA6
IMRF2
PLLT2
divnA7
GPO3
divr10
FMtc2
fracA2
CPAl2
Programming information
ADC2
Vthr2
IredL
divr2
2
FMAGCmodeV1
AMAGCmodeV1
CompDACtest0
ADCautomode
MixinFMAM
VCOMag1
ADCDAC1
VDD_korr
MaskSet1
RCfreq_1
GPIO2hl
DAC1A2
DAC2A2
DAC2off
AMfiltA1
GPIOen
Mixout1
divnA14
PLLtest
GPIO2
IMRG1
divVA6
divnA6
CPAh0
IMRF1
PLLT1
FMtc1
fracA1
CPAl1
ADC1
Vthr1
divr9
divr1
1
CompDACdisable
FMAGCmodeV0
AMAGCmodeV0
IFsection_pwr
IFin1_AM_FM
VDD_int_ext
AMLNApwrA
Temp_pwr
VCOMag0
ADCDAC0
MaskSet2
RCfreq_0
GPIO1hl
DAC1A1
DAC2A1
DAC1off
divnA13
AMfiltA0
Mixout2
PLLpwr
IMRG0
divVA0
divnA5
GPIO1
IMRF0
PLLT0
fracA0
FMtc0
CPAl0
ADC0
Vthr0
PWR
divr8
divr0
LSB
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