TEA6848HL/V3S,518 NXP Semiconductors, TEA6848HL/V3S,518 Datasheet - Page 12

• Manufacturer Part Number: TEA6848HL/V3S,518
• Description: IC TUNER CAR RADIO 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of TEA6848HL/V3S,518

• Modulation Or Protocol: AM, FM, WB
• Applications: AM/FM Radio Receiver
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 5V, 8.5V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Frequency: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Current - Receiving: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935288832518

NXP Semiconductors
TEA6848HL_4
Product data sheet
8.3 Write mode: data byte 1
8.4 Write mode: data byte 2
8.5 Write mode: data byte 3
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Bit
7
6 to 0
Bit 7
PLL7
Bit
7 to 0
Bit 7
MUTE
Bit
7
6 to 0
Bit 7
IFMT
Bit
7
6 to 4
Symbol
MUTE
DAA[6:0] setting of antenna digital auto alignment
Symbol
IFMT
FREF[2:0] reference frequency for synthesizer. These 3 bits determine the
Description of data byte 0 bits
Format of data byte 1
Description of data byte 1 bits
Format of data byte 2
Description of data byte 2 bits
Format of data byte 3
Description of data byte 3 bits
Bit 6
PLL6
Bit 6
DAA6
Bit 6
FREF2
Symbol
AF
PLL[14:8]
Symbol
PLL[7:0]
Description
FM audio mute. If MUTE = 0, then FM audio not muted. If MUTE = 1, then
FM audio muted; writing to programmable divider and antenna DAA enabled.
Rev. 04 — 29 January 2010
Description
IF measuring time. If IFMT = 0, then IF measuring time is 20 ms. If
IFMT = 1, then IF measuring time is 2 ms.
reference frequency, see
Bit 5
PLL5
Bit 5
DAA5
Bit 5
FREF1
New in car entertainment car radio tuner IC (NICE-PACS)
Description
alternative frequency. If AF = 0, then normal operation.
If AF = 1, then AF (RDS) update mode.
setting of programmable counter of synthesizer PLL.
Upper byte of PLL divider word.
Description
setting of programmable counter of synthesizer PLL. Lower
byte of PLL divider word.
Bit 4
PLL4
Bit 4
DAA4
Bit 4
FREF0
Table
Bit 3
PLL3
Bit 3
DAA3
Bit 3
IFPR
13.
Bit 2
PLL2
Bit 2
DAA2
Bit 2
BND1
TEA6848HL
Bit 1
PLL1
Bit 1
DAA1
Bit 1
BND0
© NXP B.V. 2010. All rights reserved.
Bit 0
PLL0
Bit 0
DAA0
Bit 0
AMFM
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