TEA5766UK/N1-G ST-Ericsson Inc, TEA5766UK/N1-G Datasheet - Page 16

• Manufacturer Part Number: TEA5766UK/N1-G
• Description: IC FM STEREO RADIO W/RDS 25WLCSP
• Manufacturer: ST-Ericsson Inc

Specifications of TEA5766UK/N1-G

• Frequency: 76MHz ~ 108MHz
• Sensitivity: -111dBm
• Modulation Or Protocol: FM
• Applications: FM Radio Receiver
• Current - Receiving: 17mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.6 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 25-WLCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Data Rate - Maximum: -
• Other names: 935281564023

NXP Semiconductors
TEA5766UK_1
Product data sheet
8.1.1 Interrupt clearing
8.1.2 Timing
8.1.3 Reset
The interrupt flag register contains the flags set according to the behavior outlined in
Section
(hardware interrupt line) depending on the status of the corresponding mask bit in
A logic 1 in the mask register enables the hardware interrupt for that flag.
Hence it is conceivable that, with all the mask bits cleared, the software could operate in a
polling mode by a continuous read operation of the interrupt flag register to look for bits
being set.
Interrupt mask bits are always cleared after reading the first two bytes of the interrupt
register. This is to control multiple hardware interrupts (see
a different function and is not cleared after reading the interrupt register bytes (see
Section
The interrupt flag and mask bits are always cleared after:
The timing sequence for the general operation interrupts is shown in
a read access of the interrupt bytes INTFLAG and INTMSK and a subsequent (though not
necessarily immediate) write to the mask register. It also indicates two key timing points A
and B.
If an interrupt event occurs while the register is being accessed (after point A) it must be
held until after the mask register is cleared at the end of the read operation (point B).
Point A is situated after the R/W bit has been decoded and point B is where the
acknowledge has been received from the master (host processor, etc.) after the first two
bytes have been sent.
The LOW time for the INTX line (t
However it can be shorter if the read of the INTREG registers occurs within the t
A reset can be performed (at any time) by a simple read of the interrupt bytes (byte 0R
and byte 1R), which automatically clears the interrupt flags and masks.
•
•
They have been read via the control interface
A power-on reset
8.2. When these flags are set they can also cause the INTX to go active
8.2.3).
Rev. 01 — 22 March 2007
p
) has a maximum value specified in
Figure
TEA5766UK
Stereo FM radio + RDS
6). Bit LSYNCMSK has
Figure 6
Section
© NXP B.V. 2007. All rights reserved.
and shows
13.4.
p
.
Table
15 of 59
8.