ATA5724P3-TKQY Atmel, ATA5724P3-TKQY Datasheet - Page 24
![IC RCVR ASK/FSK UHF 20-SSOP](/photos/6/91/69198/453-20-ssop_sml.jpg)
ATA5724P3-TKQY
Manufacturer Part Number
ATA5724P3-TKQY
Description
IC RCVR ASK/FSK UHF 20-SSOP
Manufacturer
Atmel
Datasheet
1.ATA5723-DK.pdf
(46 pages)
Specifications of ATA5724P3-TKQY
Frequency
433MHz
Sensitivity
-113dBm
Data Rate - Maximum
10 kbps
Modulation Or Protocol
ASK, FSK
Applications
General Purpose
Current - Receiving
11mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SOIC (0.200", 5.30mm Width)
Operating Temperature (min)
-40C
Operating Temperature (max)
105C
Operating Temperature Classification
Industrial
Product Depth (mm)
4.4mm
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Memory Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATA5724P3-TKQY
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
10.2
Figure 10-4. Controlled Noise Suppression
24
Serial bi-directional
Controlled Noise Suppression by the Microcontroller
ATA5723/ATA5724/ATA5728
POLLING/_ON
data line
(DATA_CLK)
Bit-check
mode
Bit check ok
Figure 10-3. Occurrence of a Pulse at the End of the Data Stream
Digital noise appears at the end of a valid data stream if the bit Noise_Disable (see
on page
must be set to low. The receiver remains in receiving mode. The OFF command then causes a
change to start-up mode. The programmed sleep time (see
cuted because the level at pin POLLING/_ON is low; however, the bit check is active in this
case. The OFF command also activates the bit check if the pin POLLING/_ON is held to low.
The receiver changes back to receiving mode if the bit check was successful. To activate the
polling mode at the end of the data transmission, the pin POLLING/_ON must be set to high.
This way of suppressing the noise is recommended if the data stream is not Manchester or
Bi-phase coded.
Data_out (DATA)
Preburst
DATA_CLK
Dem_out
27) in the OPMODE register is set to 0. To suppress the noise, the pin POLLING/_ON
Data
Receiving mode
Digital Noise
'1'
data clock control
Timing error
Receiving mode,
Data stream
logic active
OFF-command
'1'
'1'
Start-up
mode
t
ee
T
< T
ee
Lim_min
Bit-check
mode
Bit check ok
or T
T
pulse
Lim_max
Preburst
< t
ee
Receiving mode
Table 11-7 on page
< t
Data
Bit-check mode
Lim_min_2T
Digital noise
or t
Digital Noise
ee
> T
Lim_max_2T
27) is not exe-
9106E–RKE–07/08
Sleep
mode
Table 11-9