AD8346ARUZ Analog Devices Inc, AD8346ARUZ Datasheet - Page 12

• Manufacturer Part Number: AD8346ARUZ
• Description: IC QUADRATURE MOD .8GHZ 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD8346ARUZ

• Function: Modulator
• Lo Frequency: 800MHz ~ 2.5GHz
• Rf Frequency: 800MHz ~ 2.5GHz
• P1db: -3dBm
• Noise Floor: -147dBm/Hz
• Output Power: -6dBm
• Current - Supply: 55mA
• Voltage - Supply: 2.7 V ~ 5.5 V
• Test Frequency: 1.9GHz
• Package / Case: 16-TSSOP
• Frequency Range: 0.8GHz To 2.5GHz
• Rf Type: Quadrature
• Supply Voltage Range: 2.7V To 5.5V
• Rf Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD8346
INTERFACE TO AD9761 T
Figure 28 shows a dc-coupled current output DAC interface.
The use of dual-integrated DACs, such as the AD9761 with
specified ±0.02 dB and ±0.004 dB gain and offset matching
characteristics, ensures minimum error contribution (over
temperature) from this portion of the signal chain. The use of a
precision thin-film resistor network sets the bias levels precisely
to prevent the introduction of offset errors, which increase LO
feedthrough. For instance, selecting resistor networks with a
0.1% ratio matching characteristics maintains 0.03 dB gain and
offset matching performance.
Using resistive division, the dc bias level at the I and Q inputs
to the AD8346 is set to approximately 1.2 V. Each of the four
current outputs of the DAC delivers a full-scale current of
INPUTS
DATA
DAC
SELECT
WRITE
CLOCK
DVDD
+5V
CONTROL
DCOM
MUX
X
LATCH
LATCH
SLEEP
DAC®
Q
I
AD9761
2 ×
2 ×
R
2k Ω
SET
FS ADJ
AVDD
DAC
DAC
Figure 28. AD8346 Interface to AD9761 TxDAC
Q
I
REFIO
0.1 μ F
QOUTA
QOUTB
IOUTA
IOUTB
Rev. A | Page 12 of 20
100 Ω
100 Ω
100 Ω
100 Ω
C
FILTER
10 mA, giving a voltage swing of 0 V to 1 V (at the DAC
output). This results in a 0.5 V p-p swing at the I and Q inputs
of the AD8346 (resulting in a 1 V p-p differential swing).
Note that the ratio matching characteristics of the resistive
network, as opposed to its absolute accuracy, is critical in
preserving the gain and offset balance between the I and Q
signal path.
By applying small dc offsets to the I and Q signals from the
DAC, the LO suppression can be reduced from its nominal
value of −42 dBm to as low as −60 dBm while holding to
approximately −50 dBm over temperature (see Figure 12 for
a plot of LO feedthrough over temperature for an offset
compensated circuit).
500 Ω
500 Ω
C
500 Ω
FILTER
500 Ω
500 Ω
5V
500 Ω
0.5V p-p EACH PIN
634 Ω
500 Ω
WITH V
500 Ω
CM
0.1 μ F
= 1.2V
QBBN
IBBP
IBBN
QBBP
VPS1
SPLITTER
PHASE
VPS2
AD8346
Σ
VOUT
LOIP
LOIN