SA601DK,112 NXP Semiconductors, SA601DK,112 Datasheet - Page 5

• Manufacturer Part Number: SA601DK,112
• Description: IC LNA MIXER 1GHZ 20SSOP
• Manufacturer: NXP Semiconductors

Specifications of SA601DK,112

• Package / Case: 20-SSOP
• Frequency: 1GHz
• Number Of Mixers: 1
• Gain: 11.5dB
• Noise Figure: 1.6dB
• Current - Supply: 7.4mA
• Voltage - Supply: 2.7 V ~ 5.5 V
• Maximum Input Frequency: 1200 MHz
• Maximum Power Dissipation: 980 mW
• Mounting Style: SMD/SMT
• Maximum Power Gain: 8 dB
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Rf Type: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935164740112; SA601DK; SA601DK

Philips Semiconductors
CIRCUIT TECHNOLOGY
LNA
Impedance Match: Intrinsic return loss at the input and output ports
is 7dB and 9dB, respectively. With no external matching, the
associated LNA gain is 10dB and the noise figure is 1.4dB.
However, the return loss can be improved at 881MHz using
suggested L/C elements (Figure 5) as the LNA is unconditionally
stable.
Noise Match: The LNA achieves 1.6dB noise figure at 881MHz
when S
decrease the NF and increase S
Temperature Compensation: The LNA has a built-in temperature
compensation scheme to reduce the gain drift to 0.003dB/ C from
–40 C to +85 C.
Supply Voltage Compensation: Unique circuitry provides gain
stabilization over wide supply voltage range. The gain changes no
more than 0.5dB when V
LO Drive Level: Resistor R1 can be replaced by an inductor of
4.7nH and C3 should be adjusted to achieve a good return loss at
the LO port. Under this condition, the mixer will operate with less
than -10dBm LO drive.
2004 Dec 14
1GHz low voltage LNA and mixer
** *
LNA IN
**
11
J1
*
J2
EXT LO
SEE MIXER POWER GAIN NOTE BELOW
SPIRAL INDUCTORS ON NATURAL FR-4, 62 MILS THICK
SEE MIXER FILTER INTERFACE NOTE BELOW
= -10dB. Further improvements in S
(-7dBm, 964MHz)
C2
2.7pF
100pF
C1
CC
100pF
C3
w = 10 mils
L = 535 mils
increases from 3V to 5V.
w = 15 mils
L = 110 mils
21
.
1 F
C15
**
100
R1
L1
56nH
100pF
11
C4
will slightly
10
1
2
3
4
5
6
7
8
9
U1
SA601
Vcc
GND
LNA IN
GND
GND
GND
MIXER PD
GND
LO IN
LO IN
Figure 3. Application Circuit
5
IP3 Performance: C9 between Pin 16 and ground can be removed
to introduce 3dB mismatch loss, while improving the IP3 to +3dBm.
The associated noise figure is 11dB.
Mixer
Input Match: The mixer is configured for maximum gain and best
noise figure. The user needs to supply L/C elements to achieve this
performance.
Power Gain: The gain can be increased by approximately 1.5dB by
placing R2 across C7, instead of C5.
Power Down: The mixer can be disabled by connecting Pin 7 to
ground. When the mixer is disabled, 3mA is saved.
Power Combining: The mixer output circuit features passive
power combining (patent pending) to optimize conversion gain and
noise figure performance without using extra DC current or
degrading the IP3. For IF frequencies significantly different than
83MHz, the component values must be altered accordingly.
Filter Interface: For system integration where a high impedance
filter of 1k is to be cascaded at the mixer IF output, capacitors C5
and C6 need to be changed to 27pF and 1000pF, respectively.
100nF
MIXER OUT
MIXER OUT
C14
MIXER IN
LNA OUT
V
GND
GND
GND
GND
CC
Vcc
Vcc
100pF
C13
20
19
18
17
16
15
14
13
12
11
V
CC
w = 15 mils
L = 95 mils
100pF
270nH
C11
w = 15 mils
L = 190 mils
8.2pF
C6
L3
470nH
L2
w = 10 mils
L = 535 mils
4.7pF
2.2k
C9
R2
18pF
C5
*
33pF
C7
2.2pF
C12
**
100pF
C10
(50 , 83MHz)
MIXER OUT
LNA OUT
J3
SA601
MIXER IN
J5
Product data
J4
SR00060
C8
100nF
** *
V
CC