AD608ARZ Analog Devices Inc, AD608ARZ Datasheet - Page 9

• Manufacturer Part Number: AD608ARZ
• Description: IC MIXER/LIMITER IF 3V 16-SOIC
• Manufacturer: Analog Devices Inc
• Series: AD608r

Specifications of AD608ARZ

• Rf Type: FM, GSM, PM, PHS, FM
• Frequency: 500MHz
• Number Of Mixers: 1
• Gain: 24dB
• Noise Figure: 16dB
• Secondary Attributes: Down Converter
• Current - Supply: 7.3mA
• Voltage - Supply: 2.7 V ~ 5.5 V
• Package / Case: 16-SOIC (0.154", 3.90mm Width)
• Supply Voltage Range: 3V To 5.5V
• Rf Ic Case Style: SOIC
• No. Of Pins: 16
• Operating Temperature Range: -25°C To +85°C
• Msl: MSL 1 - Unlimited
• Ic Function: Mixer/Limiter/RSSI Receiver IF Subsystem
• Termination Type: SMD
• Supply Voltage Min: 2.7V
• Rohs Compliant: Yes
• Operating Supply Voltage: 3V
• Operating Temperature (max): 85C
• Filter Terminals: SMD
• Digital Ic Case Style: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

THEORY OF OPERATION
The AD608 consists of a mixer followed by a logarithmic IF
strip with RSSI and hard-limited outputs (see Figure 22).
MIXER
The mixer is a doubly balanced, modified gilbert-cell mixer. Its
maximum input level for linear operation is either ±56.2 mV,
regardless of the impedance across the mixer inputs, or −15 dBm
for a 50 Ω input termination. The input impedance of the mixer
can be modeled as a simple parallel RC network; the resistance
and capacitance values vs. frequency are listed in Table 5. The
bandwidth from the RF input to the IF output at the MXOP pin
is −1 dB at 30 MHz and then rapidly decreases as frequency
increases (see Figure 4).
Table 5. Mixer Input Impedance vs. Frequency
Frequency (MHz)
45
70
100
200
300
400
500
–95dBm TO
RF INPUT
–15dBm
1
2
–15dBm = ±56mV MAXIMUM FOR LINEAR OPERATION.
39.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI ACCURACY.
RFLO
RFHI
1
5
6
2.7V TO
VPS1 COM1
5.5V
1
PREAMP
2
24dB MIXER GAIN
LO
LO INPUT
–16dBm
MIXER
3
±6mA MAX OUTPUT
(±890mV INTO 165Ω)
LOHI
MIDSUPPLY
COM2
IF BIAS
4
CMOS LOGIC
DRIVER
INPUT
BPF
BIAS
VMID
MXOP
16
PRUP
Resistance (Ω)
2800
2600
1900
1200
760
520
330
7
8
330Ω
BAND-PASS
100nF
Figure 22. Functional Block Diagram
INSERTION LOSS
10.7MHz
FILTER
3dB NOMINAL
330Ω
+
Rev. C | Page 9 of 16
–75dBm TO
+15dBm
IF INPUT
18nF
100Ω
10nF
2
10
13
9
IFHI
IFLO
FDBK
MIXER GAIN
The conversion gain of the mixer is the product of its trans-
conductance and the impedance seen at Pin MXOP. For a 330 Ω
parallel-terminated filter at 10.7 MHz, the load impedance is
165 Ω, the gain is 24 dB, and the output is 15.85 × 56.2 mV (or
±891 mV) centered on the midpoint of the supply voltage. For
other load impedances, the expression for the gain in decibels is
where:
G
R
The gain of the mixer can be increased or decreased by changing
R
current at MXOP and the maximum allowable voltage swing at
Pin MXOP, which is ±1.0 V for a 3 V supply or 5 V supply.
L
L
dB
. The limitations on the gain are the ±6 mA maximum output
is the load impedance at Pin MXOP.
is the gain in decibels.
G
dB
5-STAGE IF AMPLIFIER
= 20 log
(16dB PER STAGE)
RECTIFIER CELLS
7 FULL-WAVE
110dB LIMITER GAIN
Capacitance (pF)
3.1
3.1
3.0
3.1
3.2
3.4
3.6
10
90dB RSSI
(0.0961 R
AD608
2MHz
L
LPF
)
LIMITER
FINAL
COM3
LMOP
±50µA
VPS2
RSSI
11
12
14
15
RSSI OUTPUT
20mV/dB
0.2V TO 1.8V
2.7V TO 5.5V
LIMITER
OUTPUT
400mV p-p
AD608