ISL5239KIZ Intersil, ISL5239KIZ Datasheet - Page 8

• Manufacturer Part Number: ISL5239KIZ
• Description: IC LINEARIZER PRE-DISTORT 196BGA
• Manufacturer: Intersil

Specifications of ISL5239KIZ

• Function: Pre-Distortion Linearizer
• Rf Type: CDMA2000, UMTS
• Secondary Attributes: Sample Rates to 125MSPS
• Package / Case: 196-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

pre-distorter. The pre-distorter block diagram is shown in
Figure 4.
LUT ADDR AUTO INCR.
SERIAL INPUT EN.
SER. OUTPUT EN.
Serial Interface
The serial interface for the external memory effects
calculation consists of outputs SERCLK, SERSYNC, and
SEROUT and input SERIN. The serial output sends the 32-
bit unsigned average power off-chip for further processing.
The data is transmitted via the SEROUT pin MSB first, with
the first bit marked by a high pulse on the SERSYNC pin.
The SERCLK rate is scaled such that 32 bits are transmitted
in one period of the power integrator as controlled by register
0x18 bits 5:4. SEROUT is enabled by register 0x18 bit 12.
The SERIN receives the thermal compensation parameters
from external processing using the same SERCLK and
SERSYNC used by the SEROUT. The chip expects to
receive 32 bits of data sequentially on the SERIN pin: the
MSB of A, followed by the rest of A, then the MSB of B,
followed by the rest of B. The SERIN is enabled by register
0x18 bit 8. When SERIN is disabled, registers 0x19 and
0x1a supply the A and B parameters for the thermal
compensation calculations. See Figure 16 for a detailed
timing diagram of the serial interface.
CM TEST
PWR INTGR PER.
FROM
IFIP
LUT DELTA DATA Q
LUT DELTA DATA I
COEF. B SELECT
PWR HIGH
PWR LOW
TEST
FIGURE 4. PRE-DISTORTER BLOCK DIAGRAM
Q
Q
I
I
LUT DATA Q
ACTIVE LUT
LUT DATA I
LUT ADDR
FUNC. SEL.
PD MAG.
OFFSET
SCALE
PAR. TO SERIAL
INTEGRATOR
POWER
ADDR
CALCULATION
LUT
DATA
ADDRESS
LUT
8
POWER
SERSYNC
COEF. A
SEROUT
SERCLK
MEMORY EFFECT
COMPENSATION
SERIAL TO PAR.
EXTERNAL
MEMORY
EFFECTS
FPGA
BYPASS
COEF. B
Q
I
ISL5239
IF Converter (IFC)
The output of the pre-distorter is a complex baseband signal
sampled at the system CLK rate. To provide greater system
flexibility, the IF Converter function can change this in one of
three different ways, providing frequency shifts, sample rate
changes and complex to real conversions.
Real 1X
The real 1x operating mode shifts the signal up by Fs/4 and
performs a complex to real conversion without changing the
base sample rate. This mode has 1/2 the bandwidth of the
original input signal, with the I output channel active and the
Q output channel set to 0. The operation of the IF converter
in this mode is shown in Figure 5.
Real 2X
The real 2x operating mode converts complex to real at 2x
the sample rate and shifts the signal up to Fs/2 (Fs/4 of the
output rate). This mode has the same bandwidth as the
original signal with the I channel carrying the first of twwo
samples/clock and the Q channel carrying the second
sample. The operation of the IF Converter in this mode is
shown in Figure 6.
FROM
FROM
FIGURE 6. IF CONVERTER IN REAL 2X MODE OPERATION
PD
PD
Q
Q
FIGURE 5. IF CONVERTER IN REAL 1X MODE OPERATION
I
I
2
2
FILTER
FILTER
BAND
BAND
HALF
HALF
e
e
BYPASS
BYPASS
j(pi/2)(n)
j(pi/2)(n)
Re{*}
Re{*}
Z
-1
2
2
Q
I
I