AD9861BCPZ-50 Analog Devices Inc, AD9861BCPZ-50 Datasheet - Page 40

IC FRONT-END MIXED SGNL 64-LFCSP

AD9861BCPZ-50

Manufacturer Part Number
AD9861BCPZ-50
Description
IC FRONT-END MIXED SGNL 64-LFCSP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9861BCPZ-50

Rf Type
WLL, WLAN
Features
10-bit ADC(s), 10-bit DAC(s)
Package / Case
64-LFCSP
Supply Voltage Range
2.7V To 3.6V
Logic Case Style
LFCSP
No. Of Pins
64
Operating Temperature Range
-40°C To +85°C
Msl
MSL 3 - 168 Hours
Termination Type
SMD
Interface
SPI
No. Of Channels
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Frequency
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
AD9861BCPZ-50
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9861
Register Bit
Register 17: Auxiliary Converters
Registers 18/19 : AuxADC
Registers 1A–21: AuxADC
Register 22: AuxADC
Bits 7–2: AuxDAC A FS/AuxDAC B
FS/AuxDAC C FS
Bit 1: AuxADC Ref Enable
Bit 0: AuxADC Ref FS
Bit 7: Start Average AuxADC A/
Start Average AuxADC B
Bit 7: Number of AuxADC A/
AuxADC B Samples
Bit 7: AuxSPI (Enable)
Bit 6: Sel 2not1
Bits 5, 2: Refsel B/A
Bit 1: Select A
Bit 3, 0: Start B/A
Description
These register bits independently scale the full-scale output voltage for the AuxDACs. If the full-
scale voltage is programmed to a value greater than PLL_VDD – 0.2 V, the AuxDAC becomes
nonlinear in this region.
This bit enables the on-chip, supply independent reference for the AuxADC. By default, the AuxADC
uses the PLL_AVDD supply for its full-scale voltage level.
When the AuxADC Ref Enable bit is set high, this bit allows the user to select the full-scale value of
the AuxADC. A low setting sets the full-scale value to 3.0 V; a high setting sets the full-scale value to
2.5 V. If the full-scale voltage is programmed to a value greater than PLL_VDD – 0.2 V, the AuxADC is
not linear in this region.
These registers are used to initiate a conversion cycle of the AuxADCs for a number of consecutive
samples and then report the average result. The number of consecutive samples is programmed in
the number of AuxADC A/AuxADCB samples register. The external pin Aux_SPI_CS can be config-
ured to allow it to initiate the start average conversion cycle. The result is placed in the appropriate
register corresponding to the AuxADC output [Registers 0x1A to 0x21].
These bits control the number of samples that the AuxADC collects and uses to calculate an
average value. This register is used in conjunction with the start average AuxADC register.
These 10-bit, offset binary registers are read-only and store the last corresponding AuxADC output
values. The AD9861 has two AuxADC SAR converters: AuxADC A and AuxADC B. AuxADC A has a
multiplexed input, which allows the user to select either input by using the Select A register. The 10
bits are broken into two registers, one containing the upper eight bits and the other containing the
lower two bits.
Enables the AuxSPI, which can be used to initiate a conversion and read back one of the AuxADCs.
If the auxiliary serial port is used, this bit selects which AuxADC, 1 or 2, uses the dedicated auxiliary
serial port. By default (low setting), the auxiliary serial port controls AuxADC A. Setting this bit high
allows the auxiliary serial port to control AuxADC B.
By default, the AuxADCs use an external reference applied to the AUX_REF pin. This voltage acts as
the full-scale reference for the selected AuxADC. Either AuxADC can use an internally generated
reference, which can be a buffered version of the analog supply voltage or a supply independent,
3.0 V or 2.5 V internal reference. To enable use of the internal reference for either of the AuxADCs,
set the respective Refsel register high. For internal reference configuration, see Register 17.
This bit is used to select which of the two inputs is connected to the AuxADC. By default (setting
low), the AUX_ADC_A2 (Aux2 pin) is connected to AuxADC A. Setting the respective bit high
connects the AUX_ADC_A1 (Aux1 pin) to AuxADC A.
Setting either of these bits to high initiates a conversion of the respective AuxADC, A or B. The
register bit always reads back a low.
MSB, LSB
000
001
010
011
100
101
110
111
MSB, LSB
00
01
10
11
Rev. 0 | Page 40 of 52
Number of Samples to Average
1
2
4
8
16
32
64
Not Used
AuxDAC Full-Scale Output Voltage
3.0 V
3.3 V
2.5 V
2.7 V

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