DR-TRC101-315-DK RFM, DR-TRC101-315-DK Datasheet - Page 26

• Manufacturer Part Number: DR-TRC101-315-DK
• Description: RFIC TRANCEIVER DEVELOPMENT KIT
• Manufacturer: RFM
• Type: Transceiver, SRRr

Specifications of DR-TRC101-315-DK

• Frequency: 315MHz
• For Use With/related Products: TRC101-315
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 583-1051

FIFO and RESET Mode Configuration Register
The Data FIFO Configuration Register configures:
Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that
identifies the bits to be written to the Data FIFO Configuration Register.
Bit [7..4] – FIFO Fill Bit Count: This sets the number of bits that are received before generating an
external interrupt to the host processor that the receive FIFO data is ready to be read out. It is possible to
set the maximum fill level to 15, but the designer must account for the processing time it will take to read
out the data before a register overrun occurs, at which data will be lost. It is recommended to set the fill
value to half of the desired number of bits to be read to ensure enough time for additional processing.
See Status Register for description of FIFO status bits that may be read and FIFO Read Register for
polling and interrupt-driven FIFO reads from the SPI bus.
Bit [3] – Not Used. Write a “0”.
Bit [2] – FIFO Fill Start Condition: This bit sets the condition at which the FIFO begins filling with data.
When set, the FIFO will continuously fill regardless of noise or good data. When clear, the FIFO will fill
when it recognizes the synchronous pattern as defined internally. The internal pattern is 2DD4h.
Bit [1] – Synchronous Pattern FIFO Fill: When set, the FIFO will begin filling with data when it detects
the synchronous pattern as defined in Bit [2]. The FIFO fill stops when this bit is cleared. To restart the
synchronous pattern recognition, simply clear the bit and set again.
Bit [0] – Disable RESET Mode: When cleared, if the TRC101 encounters a 0.2V spike in the power
supply, the glitch could cause a system reset. When set, this mode is disabled.
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Bit
15
1
Bit
14
Note: This pattern is not configurable and is not accessible to a host processor.
1
•
•
•
•
Note: Clearing this bit will issue a FIFO reset. See Figure 9 for FIFO write and reset
configuration.
Bit
13
0
FIFO fill interrupt condition
FIFO fill start condition
FIFO fill on synchronous pattern
RESET Mode
Bit
12
0
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Bit
11
1
Bit
10
0
Figure 9. FIFO Write and Reset Configuration
Bit
9
1
Bit
8
0
FINT3
Bit
7
FINT2
Bit
6
[POR=CA80h]
FINT1
Bit
5
FINT0
Bit
4
Bit
3
0
FIFST
Bit
2
FILLEN
Bit
1
TRC101 - 4/8/08
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RSTEN
Bit
0