DR-TRC101-315-DK RFM, DR-TRC101-315-DK Datasheet
DR-TRC101-315-DK
Specifications of DR-TRC101-315-DK
Related parts for DR-TRC101-315-DK
DR-TRC101-315-DK Summary of contents
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... Programmable Crystal Load Capacitance • Programmable Data Rate • Integrated Clock & Data Recovery • Programmable FSK Deviation Polarity • External Wake-up Events www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. DEVELOPMENT KIT (Info Click TRC101 300-1000 MHz Transceiver 16-TSSOP package • Support for Multiple Channels • ...
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... Battery Detect Threshold and Clock Output Register 5.0 Maximum Ratings.................................................................................................. 31 6.0 DC Electrical Characteristics ............................................................................... 31 7.0 AC Electrical Characteristics ............................................................................... 32 8.0 Receiver Measurement Results ........................................................................... 35 9.0 Transmitter Measurement Results....................................................................... 36 Reflow Profile .............................................................................................................. 37 10.0 Package Information ........................................................................................... 38 www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Table of Contents .......................................................................... 15 .................................................. 16 [POR=C4F7h] ........................................................... 18 [POR=9800h] ................................................................................ 19 .................................................................. 20 [POR=A680h] ...
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... Configuration Register) in order to minimize the external component count. The crystal is used as the reference for the PLL, which generates the local oscillator frequency. The accuracy requirements for production tolerance, temperature drift and aging can be determined from the maximum allowable local oscillator frequency error. Whenever a low frequency error is essential for the application possible to “ ...
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... The RF pins are high impedance and differential. The optimum differential load for the RF port at a given frequency band is shown in Table 1. TRC101 Admittance 315 MHz 1.5e-3 – j5.14e-3 433 MHz 1.4e-3 – j7.1e-3 868 MHz 2e-3 – j1.5e-2 www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Figure 1. Typical Application Circuit TABLE 1. Impedance (Ohm j179 27 + j136 8.7 + j66 L 98nH 52nH 12 ...
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... L3 Antenna Design Considerations The TRC101 is designed to drive a differential output such as a Dipole antenna or a Loop. The loop antenna is ideally suited for applications where compact size is required. The dipole is typically not an attractive option for compact designs due to its inherent size at resonance and distance needed away from a ground plane efficient antenna ...
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... Assembly View Top Side Bottom Side www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Page TRC101 - 4/8/08 ...
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... The output power amplifier is an open-collector, differential output with programmable output power which can directly drive a loop or dipole antenna, and with proper matching may also drive a monopole antenna. Incorporated in the power amplifier is an automatic antenna tuning circuit to avoid manual tuning during production and to offset “ ...
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... The preamble may be one byte (Fast CR lock) or two bytes (Slow CR lock). The next two bytes should be the synchronous pattern. In this case, data storage begins immediately following the 2 other following bytes are treated as data. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. SYNCH BYTE 0x2D SYNCH BYTE 0XD4 ...
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... An alternative method of reading the FIFO is through an SPI bus Status Register read. The drawback to this is that all interrupt and status bits must be read first before the FIFO bits appear on the bus. This could pose a problem for receiving large amounts of data ...
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... The external capacitor value will control the received ASK data rate allowed so choosing a lower value capacitor enables recovery of faster data at the expense of amplitude. Using pin (15) with a sensitive comparator will yield good results. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Input Power vs RSSI Voltage -102 ...
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... The integrated low battery detector monitors the voltage supply against a preprogrammed value and generates an interrupt when the supply voltage falls below the programmed value. The detector circuit has 50mV of hysteresis built in. SPI Interface www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Figure 6. Duty Cycle Mode Timing Page TRC101 - 4/8/08 ...
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... SPI bus. Typical SPI devices are configured for byte write operations. The TRC101 uses word writes so the nCS pin(3) should be pulled low for 16 bits. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Figure 3. SPI Interface Timing Page ...
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... RECV CTRL BASEBAND FIFO READ FIFO/RESET CONFIG DATA RATE SET POWER MANAGEMENT WAKE- PERIOD DUTY CYCLE SET BATT DETECT www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Bit Bit Bit Bit Bit Bit FIFEMP RSSI/AT GDQD DATEN FIFEN AUTO1 AUTO0 MODP DEV3 TX7 ...
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... To read the status register, initiate a command beginning with a ‘0’ and read the remaining bits on the SDO line. All other commands begin with a ‘1’ so the TRC101 recognizes a command vs. status. See figure 4 for timing reference. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Bit ...
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... Email: info@rfm.com ©by RF Monolithics, Inc. Figure 4. Status Read Timing Page TRC101 - 4/8/08 ...
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... PCB layout. See Table 4 below for load capacitance configuration. CAP3 www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Bit Bit Bit Bit DATEN FIFEN BAND1 TABLE 3. Frequency Band BAND1 BAND0 315 ...
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... Mode(1,1) – This setting is best used when receiving from a single transmitter. The measured offset value is kept independent of the state of the VDI signal. Once the link is aligned it may be manually toggled by the user. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. [POR=C4F7h] Bit Bit ...
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... PLL that tunes the desired carrier frequency. Bit [0] – Offset Frequency Enable: This bit, when set, enables the TRC101 to calculate the offset frequency by the sample taken from the Automatic Frequency Adjustment circuit. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. continued) TABLE 6. Freq Offset Range ...
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... Bit [2..0] – Output Transmit Power: These bits set the transmit output power. The output power is programmable from Max to -21dB in -3dB steps. See Table 8 below for Output Power settings. Output Power (Relative) www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. [POR=9800h] Bit Bit ...
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... The SDO pin (4) may be used as a “Transmit Register Empty” flag to write the next byte. Figure 6 shows the timing sequence. nCS SCK SDI COMMAND SDO Figure 6. Sequential Byte Write Timing www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Bit Bit Bit Bit Bit 10 9 ...
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... To calculate the center frequency fc, use Table 9 below and the following equation: where f = decimal value of Freq[11..0] = 96<f VAL www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. [POR=A680h] Bit Bit Bit Bit ...
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... Bit [9..8] – Valid Data Detector Response Time: When Pin 16 is selected as Valid Data Detector output these bits set the response time in which the TRC101 will detect the incoming synchronous bit pattern and issue an interrupt to the host processor. See Table 11 below for response settings. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. [POR=9080h] Bit ...
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... There are eight (8) predefined thresholds that can be set. See Table 14 below for settings. RSSI Thresh The RSSI threshold is affected by the LNA gain set value. Calculate the true RSSI set threshold when the LNA gain is set to a value other than 0 dB as: RSSI = RSSIthres + |GainLNA| www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Table 12. BB2 BB1 BB0 ...
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... Data Quality Detector to report good signal quality in the case that the bit rate is close to the deviation. As the data rate << deviation, a higher threshold parameter is permitted and may report good signal quality. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Bit Bit ...
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... D 7 nFSEL nFINT Figure 8. Recommended FIFO Read Method Timing *NOTE: The internal FIFO cannot be accessed faster than f FIFO or data errors will occur. For a 10MHz ref xtal the max SCK <2.5MHz. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Bit Bit Bit Bit Bit ...
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... See Status Register for description of FIFO status bits that may be read and FIFO Read Register for polling and interrupt-driven FIFO reads from the SPI bus. Bit [3] – Not Used. Write a “0”. ...
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... To calculate the BITR[6..0] decimal value for a given bit rate, use the following formula: BITR[6..0] = 10000 / [29 * (1+PRE* where DRexp is the expected data rate and PRE is defined above. Without the prescaler, the definable data rates range from 2.694kpbs to 344.828kbps. With the prescaler enabled, the definable data rates range from 337 bps to 43.103kpbs. ...
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... See Battery Detect Threshold and Clock Output Register section for programming details. NOTE: If this bit is cleared, the oscillator will continue to run even though the Crystal Oscillator Enable bit (3) is cleared and the device will not fully enter sleep mode. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. [POR=8208h] Bit Bit ...
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... Bit [7..0] – Multiplier: These bits define the multiplier value as used in the above equation. The value used must be the decimal equivalent between 0 and 255. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. [POR=E196h] Bit Bit ...
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... Bit [0] – Duty Cycle Mode Enable: This bit enables the duty cycle mode when set. NOTE: The receiver must be disabled (RXEN = ‘0’ in Power Management Register) and the wake-up timer must be enabled (WKUPEN = ‘1’ in Power Management Register) for operation in this mode. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Bit Bit ...
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... The Low Battery Detect can be enabled by setting the LBDEN bit (2) of the Power Management Register and disabled by clearing the bit. The Clock Output can be enabled by setting the CLKEN bit (0) of the Power Management Register and disabled by clearing the bit. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. [POR=C000h] Bit Bit ...
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... Analog RSSI Output Level Digital input low level Digital input high level Digital input current low Digital input current high Digital output low level Digital output high level Digital input capacitance www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Notes Min -0.5 -0.5 1 -0.5 -25 ...
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... Digital output rise/fall time www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc Load = 15 pF Page TRC101 - 4/8/08 ...
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... AFA lock range RF input capacitance Analog RSSI Filter Cap Analog RSSI deviation RSSI accuracy RSSI dynamic range RSSI programmable threshold steps Digital RSSI response time Spurious emission (@ Pmax) www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Limit Notes Values min typ max 250 0 ...
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... Output power (into differential load) Open collector output DC current Reference Spur (@ Pmax) 2nd Harmonics (@ Pmax) 3rd Harmonics (@ Pmax) Antenna tuning capacitance Output Capacitance Quality factor Phase noise www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. - continued Limit Notes Values min typ max 256 15 240 ...
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... FCC Class 2 Blocking. 4- ASK using the Analog RSSI detector. ASK 5- Load equivalent to a tuned Loop or Dipole Antenna at the required operating frequency. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. continued Limit Notes Values ...
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... All data rates are based -111 -109 -107 -105 -103 -101 -99 -97 -95 -93 -91 -89 -87 -85 1200 2400 www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. -3 BER. Sensitivity vs Data Rate 315MHz 433MHz 915MHz 868MHz 4800 9600 19200 38400 Data Rate (bps) 57600 115200 Page TRC101 - 4/8/08 ...
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... Current Consumption vs Voltage at Min/Max Data Rate 14.0 115Kbps 2.4Kbps 13.0 12.0 11.0 10.0 9.0 8.0 7.0 2.2 V www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. 915MHz 868MHz 433MHz 315MHz 3.0 V 5.4 V Voltage (V) Page TRC101 - 4/8/08 ...
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... Transmitter Measurement Results The transmitter measurements were derived from the Typical Application Circuit of Figure and the layout as suggested on pgs 5- 2.2V www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Output Power vs Voltage 3.0V Voltage (V) 315MHz 433MHz 868MHz 915MHz 5.4V Page TRC101 - 4/8/08 ...
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... Current Consumption vs Voltage (Max Output Power) 27.0 25.0 23.0 21.0 19.0 17.0 15.0 2.2V www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. 915MHz 433MHz 315MHz 3.0V Voltage (V) 868MHz 5.4V Page TRC101 - 4/8/08 ...
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... IPC/JEDEC J-STD-020C REFLOW PROFILE www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Page TRC101 - 4/8/08 ...
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... Package Dimensions – 6.4x5mm 16-pin TSSOP Package (all values in mm www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Detail Gauge Plane E Symbol θ1 θ2 θ3 θ2 0. θ1 L θ3 0.25 L1 Detail Dimensions in mm Dimensions in Inches Min Nom Max Min Nom 4.30 4.40 4.50 ...