SI4136M-EVB Silicon Laboratories Inc, SI4136M-EVB Datasheet
SI4136M-EVB
Specifications of SI4136M-EVB
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SI4136M-EVB Summary of contents
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Rev. 1.1 ...
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Section Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . ...
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Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Supply Voltage Supply Voltages Difference Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply ...
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Table 3. DC Characteristics (V = 2 –40 to 85° Parameter 1 Total Supply Current 1 RF1 Mode Supply Current 1 RF2 Mode Supply Current 1 IF Mode Supply Current Standby Current 2 ...
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Table 4. Serial Interface Timing (V = 2 –40 to 85° Parameter SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time 2 ...
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S CLK D17 t en1 Figure 2. Serial Interface Timing Diagram First bit c loc ked ...
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Table 5. RF and IF Synthesizer Characteristics (V = 2 –40 to 85° Parameter XIN Input Frequency Reference Amplifier Sensitivity Phase Detector Update Frequency RF1 VCO Center Frequency ...
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Table 5. RF and IF Synthesizer Characteristics (Continued 2 –40 to 85° Parameter RF1 Harmonic Suppression RF2 Harmonic Suppression IF Harmonic Suppression RFOUT Power Level 2 RFOUT Power Level IFOUT ...
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and IF sy nthes iz ers settled to w ithin 0.1 ppm f requency error. t pup ...
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TRACE A: Ch1 FM Main Time A Marker 1.424 kHz Real 160 Hz /div 176 Hz Start Figure 6. Typical Transient Response RF1 at 1.6 GHz with 200 kHz Phase Detector Update Frequency Rev. 1.1 us 174.04471 711.00 ...
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−60 −70 −80 −90 −100 −110 −120 −130 −140 2 10 Figure 7. Typical RF1 Phase Noise at 1.6 GHz with 200 kHz Phase Detector Update Frequency Figure 8. Typical RF1 Spurious Response at 1.6 GHz ...
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Offset Frequency (Hz) Figure 9. Typical RF2 Phase Noise at 1.2 GHz with 200 kHz Phase Detector Update Frequency Figure 10. Typical RF2 Spurious Response at 1.2 ...
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−70 −80 −90 −100 −110 −120 −130 −140 −150 2 10 Figure 11. Typical IF Phase Noise at 550 MHz with 200 kHz Phase Detector Update Frequency Figure 12. IF Spurious Response at 550 MHz with ...
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tro lle rinte d Tra c e Ind uc tors ...
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Functional Description The Si4133 is a monolithic integrated circuit that performs IF and dual-band RF synthesis for wireless communications applications. This integrated circuit (IC), with minimal external components, completes the frequency synthesis function necessary communications systems. ...
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CEN TOT ---------------------------------------------------------------------- CEN PKG EXT Tables 6 and 7 summarize the characteristics of each VCO. Table 6. Si4133-BT VCO Characteristics VCO f Range C ...
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Applications where the PLL is regularly powered-down or the frequency is periodically reprogrammed minimize or eliminate the potential effects of temperature drift because the VCO is re-tuned in either case. In applications where the ambient temperature ...
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Because of the unique architecture of the Si4133 PLLs, the time required to settle the output frequency to 0.1 ppm error is only about 25 update periods. Thus, the total time after power- change ...
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Auxiliary Output (AUXOUT) The signal appearing on AUXOUT is selected by setting the AUXSEL bits in the Main Configuration register (Register 0). PWDNB Pin AUTOPDB PWDNB = 0 PWDNB = 1 450 400 350 LPWR=0 300 ...
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Control Registers Register Name Bit Bit Bit Main Configuration 1 Phase Detector Gain Power Down RF1 3 N-Divider RF2 4 0 N-Divider 5 IF N-Divider 0 ...
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Register 0. Main Configuration Address Field = A[3:0] = 0000 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name AUXSEL Bit Name 17:14 Reserved 13:12 AUXSEL [1:0] 11:10 IFDIV [1:0] ...
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Register 1. Phase Detector Gain Address Field (A[3:0]) = 0001 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name Bit Name 17:6 Reserved 5:4 K [1:0] PI 3:2 K [1:0] P2 1:0 K ...
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Register 2. Power Down Address Field (A[3:0]) = 0010 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name Bit Name 17:2 Reserved 1 PDIB 0 PDRB Note: Enabling any ...
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Register 5. IF N-Divider Address Field (A[3:0]) = 0101 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name 0 0 Bit Name 17:16 Reserved 15:0 N [15:0] IF Register 6. RF1 R-Divider Address Field (A[3:0]) = 0110 Bit ...
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Register 8. IF R-Divider Address Field (A[3:0]) = 1000 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name Bit Name 17:13 Reserved Program to zero. 12:0 R R-Divider for ...
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Pin Descriptions: Si4133-BT SDA TA GNDR GNDR GNDR GNDR RFOUT V DDR Pin Number(s) Name Description 1 SCLK Serial clock input 2 SDATA Serial data input GNDR Common ground for RF analog circuitry 4, 5 RFLC, ...
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Table 13. Pin Descriptions for Si4133 Derivatives—TSSOP Pin Number Si4133 1 SCLK 2 SDATA 3 GNDR 4 RFLD 5 RFLC 6 GNDR GNDR 10 GNDR 11 RFOUT 12 VDDR 13 AUXOUT 14 PWDNB ...
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Pin Descriptions: Si4133-BM GNDR RFLD RFLC GNDR RFLB RFLA GNDR Pin Number(s) Name Description 1, 4, 7-9, 28 GNDR Common ground for RF analog circuitry 2, 3 RFLC, RFLD Pins for inductor connection to RF2 VCO 5,6 RFLA, RFLB Pins ...
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Table 14. Pin Descriptions for Si4133 Derivatives—MLP Pin Number ...
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Ordering Guide Ordering Part Number Si4133-BM Si4133-BT Si4123-BM Si4123-BT Si4122-BM Si4122-BT Si4113-BM Si4113-BT Si4112-BM Si4112-BT Si4133 Derivative Devices The Si4133 performs both IF and dual-band RF frequency synthesis. The Si4112, Si4113, Si4122, and the Si4123 are derivatives of this device. ...
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Package Outline: Si4133- Figure 19. 24-pin Thin Small Shrink Outline Package (TSSOP) Table 16. Package Diagram Dimensions Symbol Millimeters Min Nom Max A ...
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Package Outline: Si4133-BM Figure 20. 28-Pin Micro Leadframe Package (MLP) Table 17. Package Dimensions Controlling Dimension: mm Symbol Millimeters Min Nom A — 0.90 A1 0.00 0.01 b 0.18 0.23 D 5.00 BSC D1 4.75 BSC E 5.00 BSC E1 ...
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