SI4735-B-EVB Silicon Laboratories Inc, SI4735-B-EVB Datasheet - Page 7

BOARD EVAL SI4735 VERSION B

SI4735-B-EVB

Manufacturer Part Number
SI4735-B-EVB
Description
BOARD EVAL SI4735 VERSION B
Manufacturer
Silicon Laboratories Inc
Type
Receiverr
Datasheets

Specifications of SI4735-B-EVB

Frequency
153kHz ~ 279kHz, 520kHz ~ 1.71GHz, 2.3MHz ~ 21.85MHz, 76MHz ~ 108MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
SI4735
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Table 5. 2-Wire Control Interface Characteristics
(V
Parameter
SCLK Frequency
SCLK Low Time
SCLK High Time
SCLK Input to SDIO
(START)
SCLK Input to SDIO
SDIO Input to SCLK
SDIO Input to SCLK
SCLK input to SDIO
STOP to START Time
SDIO Output Fall Time
SDIO Input, SCLK Rise/Fall Time
SCLK, SDIO Capacitive Loading
Input Filter Pulse Suppression
Notes:
DD
1. When V
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high)
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
4. The Si4734/35 delays SDIO by a minimum of 300 ns from the V
5. The maximum t
= 2.7 to 5.5 V, V
does not occur within 300 ns before the rising edge of RST.
after the first start condition.
t
as long as all other timing parameters are met.
HD:DAT
specification.
IO
= 0 V, SCLK and SDIO are low impedance.
IO
HD:DAT
= 1.5 to 3.6 V, T
Setup
Hold (START)
Setup
Hold
Setup (STOP)
has only to be met when f
4,5
A
= –20 to 85 °C)
Symbol
t
t
t
t
t
HD:STA
SU:DAT
HD:DAT
SU:STO
SU:STA
t
t
t
f
t
f:OUT
HIGH
t
LOW
t
BUF
t
SCL
C
f:IN
r:IN
SP
b
SCL
Test Condition
Rev. 1.0
= 400 kHz. At frequencies below 400 KHz, t
1,2,3
IH
threshold of SCLK to comply with the minimum
20
20
+
+
Min
100
1.3
0.6
0.6
0.6
0.6
1.3
0.1
0.1
0
0
---------- -
1pF
---------- -
1pF
C
C
b
b
Si4734/35-B20
Typ
HD:DAT
Max
400
900
250
300
50
50
may be violated
Unit
kHz
pF
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
ns
7

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