ATA556714N-DDB Atmel, ATA556714N-DDB Datasheet - Page 16

• Manufacturer Part Number: ATA556714N-DDB
• Description: IC IDIC R/W 330BIT 75PF
• Manufacturer: Atmel

Specifications of ATA556714N-DDB

• Function: Read/Write
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.1
6.2
Figure 6-1.
Table 6-1.
16
Mode
FSK1
FSK2
PSK1
PSK2
PSK3
Manchester
Bi-phase 1 (’50)
Bi-phase 2 (’57)
NRZ
Notes:
(1)
(1)
(2)
(2)
(2)
Binary Bit-rate Generator
OTP Functionality
1. A common multiple of bit rate and FSK frequencies is recommended.
2. In PSK mode the selected data rate has to be an integer multiple of the PSK sub-carrier frequency.
ATA5567
L
0
1
Block 0 — Configuration Map in Extended Mode (X-mode)
ATA5567 Types of Modulation in Extended Mode
1) If Master Key = 6 and bit 15 is set, then test mode access is disabled and extended mode is active
2) If Master Key = 9 and bit 15 is set, then extended mode is enabled
1
1
Master Key
Note 1), 2)
Unlocked
Locked
2
0
Direct Data Output Encoding
FSK/5-/8
FSK/10-/8
Phase change when input changes
Phase change on bit clock if input high
Phase change on rising edge of input
0 = falling edge, 1 = rising edge on mid-bit
“1” creates an additional mid-bit change
“0” creates an additional mid-bit change
1 = damping on, 0 = damping off
3
0
4
1
In extended mode the data rate is binary programmable to operate at any data rate between
RF/2 and RF/128 as given in the formula below.
Data rate = RF / (2n + 2)
If the OTP bit is set to “1”, all memory blocks are write protected and behave as if all lock bits are
set to 1. If the master key is set to “6” additionally, the ATA5567 mode of operation is locked for-
ever (= OTP functionality).
If the master key is set to “9”, the test-mode access allows the re-configuration of the tag again.
5
0
6
0
0 = RF/5; 1 = RF/8
0 = RF/10; 1 = RF/8
7
0
8
0
n5
9
Data Bit Rate
10 11 12
n4 n3 n2 n1 n0
RF/(2n+2)
Direct
PSK1
PSK2
PSK3
FSK1
FSK2
Manchester
Bi-phase ('50)
Bi-phase ('57)
13 14 15 16
1
0
0
0
0
0
0
0
1
1
Modulation
17 18 19 20
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
Inverse Data Output Encoding
FSK/8-/5
FSK/8-/10
Phase change when input changes
Phase change on bit clock if input low
Phase change on falling edge of input
1 = falling edge, 0 = rising edge on mid-bit
0 = damping on, 1 = damping off
“0” creates an additional mid-bit change
“1” creates an additional mid-bit change
0
0
1
1
0
0
0
0
0
0
1
0
1
0
1
0
1
0
21
PSK
0
0
1
1
CF
22
0
1
0
1
23
RF/2
RF/4
RF/8
Res
0 = RF/8; 1 = RF/5
0 = RF/8; 1 = RF/10
24
25
Block
Max
26
27
28
29
30
31
32
4874F–RFID–07/08
(= FSK1a)
(= FSK2a)