AMMC-5024-W10 Avago Technologies US Inc., AMMC-5024-W10 Datasheet - Page 8

• Manufacturer Part Number: AMMC-5024-W10
• Description: IC MMIC AMP TWA GAAS 30-40GHZ
• Manufacturer: Avago Technologies US Inc.
• Type: General Purposer

Specifications of AMMC-5024-W10

• Function: Amplifier
• Noise Figure Typ: 5.5dB
• Supply Current: 350mA
• Supply Voltage Range: 7V
• Frequency Max: 40GHz
• Frequency Min: 30kHz
• Supply Voltage Max: 10V
• Gain: 16dB
• Number Of Channels: 1
• Frequency (max): 40GHz
• Output Power: 22.5@22000MHzdBm
• Power Supply Requirement: Single
• Single Supply Voltage (max): 10V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 516-1845; AMMC-5024-W10

Biasing and Operation
AMMC-5024 is biased with a single positive drain supply
(V
mance the recommended bias is V
mA. To achieve this drain current level, V
between –2.5 to –3.5V. Typically, DC current flow for V
is –10 mA.
The AMMC-5024 has a second gate bias (Vg2) that may be
used for gain control. When not being utilized, Vg2 should
be left open-circuited.
This feature further enhances the versatility of applica-
tions where variable gain over a broad bandwidth is
necessary.
This second gate bias (Vg2) is connected to the gates of
the upper FETs in each cascode stage through a small
de-queing resistor. The other end of the gate line is termi-
nated in an on-chip resistive/diode divider network, which
allows the second gate to self-bias. Thus, with Vg2 left
open-circuited, the drain current is set by the (Vg1) gate
bias voltage applied to the lower FET in each stage.
The nominal open circuit voltage for Vg2 is approximately
2 volts. Under this operating condition, maximum gain
and power are achieved from the TWA.
By applying an external voltage to the second gate bias
(Vg2) less than the open-circuit potential, the drain volt-
age on the lower FET can be decreased to a point where
the lower FET enters the linear operating region. This
reduces the current drawn by each stage. Decreasing Vg2
further will reduce the drain voltage on the lower FET to-
wards zero while pinching off the upper FET in each stage.
At larger negative values of Vg2 (between 0 and -2.5 volts)
the gain of the TWA will decrease significantly.
Using the simplest form of assembly (Figure 20), the device
is capable of delivering flat gain over a 2 – 50 GHz range
with a minimum of gain slope and ripple. However, this
device is designed with DC coupled RF I/O ports, and
operation may be extended to lower frequencies (<2
GHz) through the use of off-chip low-frequency extension
circuitry and proper external biasing components. With
low frequency bias extension it may be used in a variety
of time-domain applications (through 40 Gb/s).
Figure 21 shows a typical assembly configuration.
8
dd
) a negative gate supply (V
g1
). For best overall perfor-
dd
=7V and I
g1
is typically
dd
= 200
g1
When bypass capacitors are connected to the AUX pads,
the low frequency limit is extended down to the corner
frequency determined by the bypass capacitor and the
combination of the on-chip 50 ohm load and small de-
queing resistor. At this frequency the small signal gain
will increase in magnitude and stay at this elevated level
down to the point where the C
an open circuit, effectively rolling off the gain completely.
The low frequency limit can be approximated from the
following equation:
f
where:
R
R
C
nected to the AUX Drain pad in farads.
With the external bypass capacitors connected to the AUX
gate and AUX drain pads, gain will show a slight increase
between 1.0 and 1.5 GHz. This is due to a series combina-
tion of C
by the parasitic inductance (L
the inductance of the bond wire (L
wire from the Aux pads to the bypass capacitors should
be made as short as possible.
Input and output RF ports are DC coupled; therefore, DC
decoupling capacitors are required if there are DC paths.
(Do not attempt to apply bias to these pads.)
RF bond connections should be kept as short as possible
to reduce RF lead inductance which will degrade perfor-
mance above 20 GHz.
An optional output power detector network is also pro-
vided. A >0.5 µF capacitor is required for the Det_Out
pad to expand power detection performance below 100
MHz.
Ground connections are made with plated through-holes
to the backside of the device; therefore, ground wires are
not needed.
Caux
DEQ
o
aux
is the 50Ω gate or drain line termination resistor.
is the capacitance of the bypass capacitor con-
is the small series de-queing resistor and 10Ω.
=
2πC
aux
aux
and the on chip resistance but is exaggerated
(Ro + R
1
DEQ
)
c
) of the bypass capacitor and
aux
bypass capacitor acts as
d
). Therefore the bond