AD8302ARU-REEL Analog Devices Inc, AD8302ARU-REEL Datasheet - Page 16

IC DETECTOR RF/IF 14-TSSOP T/R

AD8302ARU-REEL

Manufacturer Part Number
AD8302ARU-REEL
Description
IC DETECTOR RF/IF 14-TSSOP T/R
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD8302ARU-REEL

Rohs Status
RoHS non-compliant
Frequency
2.7GHz
Rf Type
General Purpose
Input Range
-60dBm ~ 0dBm
Accuracy
0.5dB
Voltage - Supply
2.7 V ~ 5.5 V
Current - Supply
23mA
Package / Case
14-TSSOP (0.173", 4.40mm Width)
Pin Count
14
Screening Level
Industrial
Package Type
TSSOP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD8302ARU-REEL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD8302
Note that by convention, the phase difference is taken in the range
from –180° to +180°. Since this style of phase detector does not
distinguish between ±90°, it is considered to have an unambiguous
180° phase difference range that can be either 0° to +180° centered
at +90° or 0° to –180° centered at –90°.
The basic structure of both output interfaces is shown in Figure 3. It
accepts a setpoint input and includes an internal integrating/averag-
ing capacitor and a buffer amplifier with gain K. External access to
these setpoints provides for several modes of operation and enables
flexible tailoring of the gain and phase transfer characteristics. The
setpoint interface block, characterized by a transresistance R
ates a current proportional to the voltage presented to its input pin,
MSET or PSET. A precise offset voltage of 900 mV is introduced
internally to establish the center-point (V
functions, i.e., the setpoint voltage that corresponds to a gain of 0 dB
and a phase difference of 90°. This setpoint current is subtracted
from the signal current, I
channel or from the phase detector in the phase channel. The result-
ing difference is integrated on the averaging capacitors at either pin
MFLT or PFLT and then buffered by the output amplifier to the
respective output pins, VMAG and VPHS. With this open-loop
arrangement, the output voltage is a simple integration of the differ-
ence between the measured gain/phase and the desired setpoint:
where I
is the setpoint input, and T is the integration time constant equal
to R
nal 1.5 pF and the external capacitor C
I
BASIC CONNECTIONS
Measurement Mode
The basic function of the AD8302 is the direct measurement of gain
and phase. When the output pins, VMAG and VPHS, are connected
directly to the feedback setpoint input pins, MSET and PSET, the
default slopes and center points are invoked. This basic connection
shown in Figure 4 is termed the measurement mode. The current
from the setpoint interface is forced by the integrator to be equal to
the signal currents coming from the log amps and phase detector.
The closed loop transfer function is thus given by:
The time constant T represents the single-pole response to the enve-
lope of the dB-scaled gain and the degree-scaled phase functions. A
small internal capacitor sets the maximum envelope bandwidth to
approximately 30 MHz. If no external C
can follow the gain and phase envelopes within this bandwidth. If
longer averaging is desired, C
ing to T (ns) = 3.3 × C
minimal overshoot, it is recommended that 1 pF minimum value
external capacitors be added to the MFLT and PFLT pins.
IN
= I
Figure 3. Simplified Block Diagram of the Output Interface
LA
F
V
V
C
OUT
OR I
OUT
AVE
FB
PD
is the feedback current equal to (V
/K, where C
=
=
(
R I
I
I R
FB
F
IN
+
(
IN
F
+
AVE
AVE
V
I
IN
FB
CP
1.5pF
, coming from the log amps in the gain
(pF). For best transient response with
) ( )
is the parallel combination of the inter-
)
R
/
/
F
FLT
(
1
sT
+
can be added as necessary accord-
V
sT
CP
K
+
= 900mV
)
FLT
CP
FLT
+
) for the gain and phase
is used, the AD8302
.
20k
SET
– V
MFLT/PFLT
VMAG/VPHS
MSET/PSET
CP
)/R
F
F
, V
, gener-
SET
(7)
(6)
C
FLT
–16–
Figure 4. Basic Connections in Measurement Mode with
30 mV/dB and 10 mV/Degree Scaling
In the low frequency limit, the gain and phase transfer functions
given in Equations 4 and 5 become:
which are illustrated in Figure 5. In Equation 8b, P
the power in dBm equivalent to V
ence impedance. For the gain function, the slope represented by
R
With a center point of 900 mV for 0 dB gain, a range of –30 dB to
+30 dB covers the full-scale swing from 0 V to 1.8 V. For the phase
function, the slope represented by R
center point of 900 mV for 90°, a range of 0° to 180° covers the
full-scale swing from 1.8 V to 0 V. The range of 0° to –180° covers
the same full-scale swing but with the opposite slope.
F
Figure 5. Idealized Transfer Characteristics for the Gain
and Phase Measurement Mode
I
SLP
V
V
V
900mV
900mV
PHS
MAG
MAG
is 600 mV/decade or, dividing by 20 dB/decade, 30 mV/dB.
1.8V
1.8V
V
V
0V
0V
INA
INB
–180
–30
=
=
=
R I
(
R I
R I
R1
R2
F SLP
F
F SLP
+10mV/DEG
Φ
C1
C4
C6
C5
C3
(
|
C7
Φ
log
–90
VP
/ 20
(
V
PHASE DIFFERENCE – Degrees
R4
(
V
INA
MAGNITUDE RATIO – dB
)
INA
1
2
3
4
5
6
7
(
P
)
COMM
INPA
OFSA
VPOS
OFSB
INPB
COMM
INA
/
V
Φ
AD8302
INA
INB
(
0
0
V
F
I
30mV/dB
and V
P
INB
Φ
)
INB
VMAG
is 10 mV/degree. With a
MSET
VPHS
MFLT
VREF
+
PSET
PFLT
)
V
V
|–
)
CP
INB
CP
+
90
14
13
12
11
10
V
–10mV/DEG
9
8
or
at a specified refer-
90
CP
°
)
+
V
INA
C8
MAG
V
CP
and P
V
PHS
V
CP
180
+30
C2
REV. A
INB
are
(8b)
(8a)
(9)

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