AD6636BC/PCB Analog Devices Inc, AD6636BC/PCB Datasheet - Page 45

• Manufacturer Part Number: AD6636BC/PCB
• Description: BOARD EVAL FOR AD6636
• Manufacturer: Analog Devices Inc

Specifications of AD6636BC/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6636
• Lead Free Status / Rohs Status: Not Compliant

Interleaved I/Q Mode
Parallel port channel mode is selected by writing 0 to the data
format bit for the parallel port in consideration. In this mode, I
and Q words from the AGC are output on the same 16-bit data
bus on a time-multiplexed basis. The 16-bit I word is output
followed by the 16-bit Q word. The specific AGCs output by the
port are selected by setting individual bits for each of the AGCs
in the parallel port control register. Figure 40 shows the timing
diagram for the interleaved I/Q mode.
When an output data sample is available for output from an
AGC, the parallel port initiates the transfer by pulling the
PxREQ signal high. In response, the processor receiving the
data needs to pull the PxACK signal high, acknowledging that it
is ready to receive the signal. In Figure 40, PxACK is already
pulled high and, therefore, the 16-bit I data is output on the
PxCH [2:0]
Px [15:0]
PxGAIN
PxACK
PxREQ
PCLK
PxIQ
PxCH [2:0]
Px [15:0]
PxGAIN
PxACK
PxREQ
PCLKn
PxIQ
Figure 40. Interleaved I/Q Mode Without an AGC Gain Word
t
Figure 41. Interleaved I/Q Mode with an AGC Gain Word
DPREQ
t
DPREQ
t
DPIC
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t
t
t
DPP
DPIQ
DPCH
I[15:0]
LOGIC LOW ‘0’
PxCH [2:0] = CHANNEL NO.
t
I [15:0]
t
PxCH [2:0] = CHANNEL NO.
DPP
DPCH
data bus on the next PCLK rising edge after PxREQ is driven
logic high. The PxIQ signal also goes high to indicate that I data
is available on the data bus. The next PCLK cycle brings the
Q data onto the data bus. In this cycle, the PxIQ signal is driven
low. When I data and Q data are output, the channel indicator
pins PxCH[2:0] indicate the data source (AGC number).
Figure 40 is the timing diagram for interleaved I/Q mode with
the AGC gain word disabled. Figure 41 is a similar timing
diagram with the AGC gain word. I and Q data are as explained
for Figure 40. In the PCLK cycle after the Q data, the AGC gain
word is output on the data bus and the PxGAIN signal is pulled
high to indicate that the gain word is available on the parallel
port. Therefore, a minimum of three or four PCLK cycles are
required to output one sample of output data on the parallel
port without or with the AGC gain word, respectively.
Q[15:0]
Q [15:0]
GAIN [11:0]
t
DPGAIN
0000 +
AD6636