78M6612-DB/OMU-USB Maxim Integrated Products, 78M6612-DB/OMU-USB Datasheet - Page 16
78M6612-DB/OMU-USB
Manufacturer Part Number
78M6612-DB/OMU-USB
Description
KIT DEMO OUTLET MEASUREMENT OMU1
Manufacturer
Maxim Integrated Products
Datasheets
1.78M6612-IMF.pdf
(111 pages)
2.78M6612-EVM-1.pdf
(58 pages)
3.78M6612-DBOMU-USB.pdf
(30 pages)
4.78M6612-DBOMU-USB.pdf
(4 pages)
Specifications of 78M6612-DB/OMU-USB
Data Bus Width
8 bit
Interface Type
USB
Tool Type
Demonstration Board
Core Architecture
8051
Cpu Core
80515
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- 78M6612-IMF PDF datasheet
- 78M6612-EVM-1 PDF datasheet #2
- 78M6612-DBOMU-USB PDF datasheet #3
- 78M6612-DBOMU-USB PDF datasheet #4
- Current page: 16 of 111
- Download datasheet (2Mb)
78M6612 Data Sheet
DS_6612_001
There is no correlation between the line signal frequency and the choice of PRE_SAMPS or SUM_CYCLES
(even though when SUM_CYCLES = 42 one set of SUM_CYCLES happens to sample a period of 16.6 ms).
Furthermore, sampling does not have to start when the line voltage crosses the zero line, and the length
of the accumulation interval need not be an integer multiple of the signal cycles.
It is important to note that the length of the accumulation interval, as determined by N
, the product of
ACC
SUM_CYCLES and PRE_SAMPS, is not an exact multiple of 1000 ms. For example, if SUM_CYCLES = 60,
and PRE_SAMPS = 00 (42), the resulting accumulation interval is:
⋅
N
60
42
2520
τ
=
=
=
=
ACC
999
.
75
ms
32768
Hz
f
2520
.
62
Hz
S
13
This means that accurate time measurements should be based on the RTC, not the accumulation
interval.
1.4 80515 MPU Core
The 78M6612 includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one
clock cycle. Using a 5 MHz (4.9152 MHz) clock results in a processing throughput of 5 MIPS. The
80515 architecture eliminates redundant bus states and implements parallel execution of fetch and
execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most of the 1-
byte instructions are performed in a single cycle. This leads to an 8x performance (in average)
improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.
Actual processor clocking speed can be adjusted to the total processing demand of the application
(measurement calculations, AMR management, memory management, LCD driver management and I/O
management) using the I/O RAM register MPU_DIV[2:0].
Typical power and energy measurement functions based on the results provided by the internal 32-bit
compute engine (CE) are available for the MPU as part of Teridian’s standard library. A standard ANSI
“C” 80515 application program library is available to help reduce design cycle.
16
Rev. 1.2
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