MAXQ3183-KIT Maxim Integrated Products, MAXQ3183-KIT Datasheet - Page 29

• Manufacturer Part Number: MAXQ3183-KIT
• Description: KIT EV REFRNC DSIGN FOR MAXQ3183
• Manufacturer: Maxim Integrated Products
• Series: MAXQ®r

Specifications of MAXQ3183-KIT

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: No
• Utilized Ic / Part: MAXQ3183
• Primary Attributes: Polyphase AFE
• Secondary Attributes: SPI Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-M3183-KIT

Bit:
Name:
Reset:
Bit:
Name:
Reset:
7:4, 1:0
7:5, 0
BIT
BIT
4
3
2
1
3
2
EXTCLK
DSPDIS
LOWPM
SWRES
CRCEN
POPOL
NAME
NAME
Low-Power, Multifunction, Polyphase AFE
—
—
______________________________________________________________________________________
—
—
7
0
7
0
Reserved.
When set, the high-frequency crystal oscillator is disabled and the XTAL1 pin is configured to be a
clock input for the device. This is used when it is desired to operate multiple devices from the same
clock source for purposes of maintaining synchronization.
When set, forces the internal software to restart from the reset vector. This has the same effect as a
power-on reset, but does not specifically reset any hardware peripherals. This bit is automatically
cleared after the reset.
When set, disables the signal processing software routines. The CPU continues to run at full speed,
but only to perform supervisory functions (such as servicing the SPI port).
When set, causes the CPU to switch its clock source from the external crystal to an internal ring oscillator
that operates at a nominal frequency of 1MHz. In this mode, the CPU continues to run, but the host must
reconfigure the parameters configured for crystal operation (such as filter settings, timeouts, and pulse
widths).
Reserved.
If set, a 1-byte CRC is appended to the end of each SPI read and is expected at the end of each SPI
write. See the SPI Communications Protocol section for details about how to use the CRC byte for error
checking on the SPI bus.
This bit sets the polarity of the output pulse generators. If clear, the pulse outputs are active low; that
is, they remain in the high state until a pulse event occurs, at which time they switch low for one
pulse-width interval before reverting to the high state. If set, the pulse outputs are active high; that is,
they remain in the low state until a pulse event occurs, at which time they switch to the high state for
one pulse-width interval before reverting to the low state.
with Harmonics and Tamper Detect
—
—
6
0
6
0
—
—
5
0
5
0
EXTCLK
Operating Mode Register 0 (OPMODE0) (0x001)
Operating Mode Register 1 (OPMODE1) (0x002)
—
0
4
4
0
FUNCTION
FUNCTION
SWRES
CRCEN
3
0
3
0
DSPDIS
POPOL
2
0
2
0
LOWPM
—
1
0
1
0
—
—
0
0
0
0
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