MAXQ3183-KIT Maxim Integrated Products, MAXQ3183-KIT Datasheet - Page 100

• Manufacturer Part Number: MAXQ3183-KIT
• Description: KIT EV REFRNC DSIGN FOR MAXQ3183
• Manufacturer: Maxim Integrated Products
• Series: MAXQ®r

Specifications of MAXQ3183-KIT

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: No
• Utilized Ic / Part: MAXQ3183
• Primary Attributes: Polyphase AFE
• Secondary Attributes: SPI Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-M3183-KIT

Low-Power, Multifunction, Polyphase AFE
with Harmonics and Tamper Detect
This register reports phase angle of voltage phase B
with respect to voltage phase A. The value is
expressed in units of 0.01 degree; thus, the nominal
value is 12000 decimal (0x2EE0). This value is calculat-
ed based on zero-crossing detection. It may exhibit
noticable error in the presence of harmonics on voltage
channels. This register is 2 bytes wide.
This register reports phase angle of voltage phase C
with respect to voltage phase A. The value is
expressed in units of 0.01 degree; thus, the nominal
value is 24000 decimal (0x5DC0). This value is calcu-
lated based on zero-crossing detection. It may exhibit
noticable error in the presence of harmonics on voltage
channels. This register is 2 bytes wide.
This register reports the RMS voltage. The units are
defined by the VOLT_CC setting. Use AUX_CFG to
configure the phase (A/B/C) and harmonic order
desired.
This register reports the harmonic RMS current of
selected phase (A/B/C) and harmonic order, harmonic,
or the RMS current of the neutral current channel. The
units are defined by the AMP_CC setting. Use
Table 7. Virtual Registers That Activate Special Commands
RMS Current, Harmonic/Neutral (I.N, I.HARM) (0x840)
100
ENTER LOWPM
ENTER STOP
EXIT LOWPM
UPD_SFR
UPD_MIR
TEMP_C
DSPVER
NAME
_____________________________________________________________________________________
RMS Voltage, Harmonic (V.HARM) (0x830)
ADDRESS
0xA00
0xC00
0xC01
0xC02
0xC03
0xC04
0x900
Phase B Phasor (VBPH: 0x852)
Phase C Phasor (VCPH: 0x854)
Reading this register copies the mirror registers (R_ADCF, R_ADCRATE,
R_ADCACQ, R_SPICF) into hardware SFR registers. The read returns dummy data.
Reading this register copies hardware SFR registers into mirror registers (R_ADCF,
R_ADCRATE, R_ADCACQ, R_SPICF). The read returns dummy data.
Reading this register returns the DSP firmware version number.
Reading this register initiates the on-chip temperature sensor conversion. Upon
completion, the temperature value is returned in degree Celsius, with a resolution of
1°C. The TEMP_CC register must be configured before reading this register.
Reading this register places the device into Stop Mode.
Reading this register places the device into LOWPM Mode.
Reading this register exits LOWPM Mode.
Harmonics
Phasors
DESCRIPTION
AUX_CFG to configure the phase (A/B/C) and harmonic
order desired.
This register reports the ratio of the selected harmonic
RMS over the fundamental RMS of the same signal
(except IN). The master must configure the AUX_CFG
register to enable the AUX channel, enable harmonics,
and select AUX_MUX before reading this register. This
register is 4 bytes wide, LSB = 2
Table 7 shows the read-only virtual registers that acti-
vate special commands when read by the master.
Some commands return dummy values.
Careful PCB layout significantly minimizes noise on the
analog inputs, resulting in less noise on the digital I/O
that could cause improper operation. The use of multi-
layer boards is essential to allow the use of dedicated
power planes. The area under any digital components
should be a continuous ground plane if possible. Keep
any bypass capacitor leads short for best noise rejec-
tion and place the capacitors as close to the leads of
the devices as possible.
The MAXQ3183 must have separate ground areas for
the analog (AGND) and digital (DGND) portions, con-
nected together at a single point.
Ratio of Harmonic/Fundamental (HARM_NF) (0x850)
Applications Information
Grounds and Bypassing
Special Commands
-16
.
LENGTH
(BYTES)
DATA
1
1
2
2
1
1
1