73M1866B-KEYCHN Maxim Integrated Products, 73M1866B-KEYCHN Datasheet - Page 34
73M1866B-KEYCHN
Manufacturer Part Number
73M1866B-KEYCHN
Description
BOARD KEYCHAIN INF DANUBE EVM
Manufacturer
Maxim Integrated Products
Datasheets
1.73M1866B-KEYCHN.pdf
(88 pages)
2.73M1866B-KEYCHN.pdf
(14 pages)
3.73M1866B-KEYCHN.pdf
(15 pages)
4.73M1866B-KEYCHN.pdf
(13 pages)
Specifications of 73M1866B-KEYCHN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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73M1866B/73M1966B Data Sheet
The R/W bit determines whether the host requests a read (1) or a write (0) operation.
The second byte of the SPI transaction is the address byte. The address byte simply contains the 8-bit
value for the register targeted by the operation. For the 73M1x66B, only six bits of the address are
relevant for the register space, and the two most-significant bits of the address byte are always set to 0.
The third byte of the SPI transaction is the data byte. It contains the data to write to the addressed
73M1x66B registers or the data read from the addressed 73M1x66B register.
In the 8-bit mode, the three bytes are exchanged over three frames, as directed by CS. Figure 16 and
Figure 17 show a write and read transaction between the 73M1x66B and the host in 8-bit mode.
34
SCLK
SDO
SDI
CS
HOST
SDO
CONTROL
Figure 16: SPI Write Operation – 8-bit Mode
Figure 15: Daisy-Chain Configuration
SCLK
SDI
CS
ADDRESS
SCLK
CS
SDO
SCLK
CS
SDO
SCLK
CS
SDO
Channel 15
73M1906B
73M1906B
73M1906B
Channel 0
SDITHRU
Channel 1
SDITHRU
SDITHRU
SDI
SDI
SDI
...
DATA [7:0]
HI-Z
CID=CIDin-1
CIDin
CID=CIDin-2
CID=000
(target)
DS_1x66B_001
Rev. 1.6
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