73S8009CN-DB Maxim Integrated Products, 73S8009CN-DB Datasheet - Page 12

• Manufacturer Part Number: 73S8009CN-DB
• Description: BOARD DEMO FOR 73S8009CN
• Manufacturer: Maxim Integrated Products

Specifications of 73S8009CN-DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

73S8009CN Demo Board User Manual
4 Design Considerations
4.1
Follow these layout rules:
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4.2
Default configuration of the Demo Board contains a 27 pF capacitor (C12) from the CLK pin of the smart
connector to ground and a 27 pF capacitor (C13) from the RST pin of the smart connector to ground.
These capacitors serve as filters for CLK and RST signals in the case of long traces or test equipment
perturbations. The capacitor on CLK reduces ringing on the trace, reduces coupling to other traces and
slows down the edge of the CLK signal. The capacitor on RST helps the perturbation specification in a
noisy environment. The filter capacitors can be useful in the EMV test environment and have no effect on
NDS testing
C9 and C12 are represented on both schematic and BOM. These capacitors are optional filter capacitors
on the smart card lines CLK and RST, respectively for each card interface. These capacitors may be
adjusted (value, not to exceed 30 pF) or removed to optimize performance in each specific application
(PCB, card clock frequency, compliance with applicable standards etc).
4.3
4.3.1 Single Supply Input Power
The single supply configuration should only connect the input power supply to VPC (2.7 V to 6.0 V).
4.3.2 Output Supply Power
The VDD output can be used to power other 3.3 V circuits (40 mA max).
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Route I/O and auxiliary signals away from card interface signals.
Keep CLK trace as short as possible and with minimal bends in the trace. Keep route of the CLK
trace to one layer (avoid vias to other layers). Keep CLK trace away from other traces especially
RST, I/O and VCC. Filtering of the CLK trace is allowed for noise purpose. Up to 30 pF to ground is
allowed at the CLK pin of the smart card connector. Also, the zero ohm series resistor, R7, can be
replaced with a small resistor for additional filtering (no more than 100 Ω).
Keep VCC trace as short as possible. Make trace a minimum of 0.5 mm thick. Also, keep VCC away
from other traces especially RST and CLK.
Keep RST trace away from VCC and CLK traces. Up to 30 pF to ground is allowed for filtering.
Keep 0.1 µF close to VDD pin of the device and directly take other end to ground.
Keep 0.1 µF and 10 µF close to VPC pin of the device and directly take other end to ground.
Keep 4.7 µF close to VP pin of the device and directly take other end to ground.
Keep 0.47 µF close to VCC pin of the smart card connector and directly take other end to ground.
The AUX1, AUX2, DP and DM signals should be isolated as much as possible as they can be used
as fast data signaling for USB operation. The DP and DM signals should be routed in parallel as
much as possible.
General Layout Rules
Optimization for Compliance with EMV
Power Supply Configurations
UM_8009CN_060
Rev. 1.1