LTC3729EG#TR Linear Technology, LTC3729EG#TR Datasheet - Page 19

• Manufacturer Part Number: LTC3729EG#TR
• Description: IC SW REG SYNC STEP-DOWN 28-SSOP
• Manufacturer: Linear Technology
• Series: PolyPhase®r
• Type: Step-Down (Buck)r

Specifications of LTC3729EG#TR

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.8 ~ 5 V
• Current - Output: 5A
• Frequency - Switching: 1.1MHz
• Voltage - Input: 4 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Other names: LTC3729EGTR

APPLICATIONS INFORMATION
400kHz. The nominal operating frequency range of the
LTC3729 is 250kHz to 550kHz.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the ex‑
ternal and internal oscillators. This type of phase detector
will not lock up on input frequencies close to the harmonics
of the VCO center frequency. The PLL hold‑in range, ∆f
is equal to the capture range, ∆f
The output of the phase detector is a complementary pair of
current sources charging or discharging the external filter
network on the PLLFLTR pin. A simplified block diagram
is shown in Figure 7.
If the external frequency (f
cillator frequency f
pulling up the PLLFLTR pin. When the external frequency is
less than f
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus the voltage on the PLLFLTR
pin is adjusted until the phase and frequency of the ex‑
ternal and internal oscillators are identical. At this stable
operating point the phase comparator output is open and
the filter capacitor C
PLLIN pin must be driven from a low impedance source
such as a logic gate located close to the pin. When us‑
ing multiple LTC3729’s for a phase‑locked system, the
PLLFLTR pin of the master oscillator should be biased at
∆f
H
PLLIN
= ∆f
EXTERNAL
OSC
Figure 7. Phase-Locked Loop Block Diagram
0SC
C
= ±0.5 f
, current is sunk continuously, pulling down
50k
0SC
FREQUENCY
DETECTOR
DETECTOR
O
DIGITAL
LP
PHASE/
PHASE
, current is sourced continuously,
(250kHz‑550kHz)
holds the voltage. The LTC3729
PLLIN
2.4V
C
) is greater than the os‑
:
PLLFLTR
R
10k
LP
3729 F07
OSC
C
LP
H
,
a voltage that will guarantee the slave oscillator(s) ability
to lock onto the master’s frequency. A DC voltage of
0.7V to 1.7V applied to the master oscillator’s PLLFLTR
pin is recommended in order to meet this requirement.
The resultant operating frequency will be approximately
500kHz.
The loop filter components (C
rent pulses from the phase detector and provide a stable
input to the voltage controlled oscillator. The filter compo‑
nents C
lock. Typically R
Minimum On-Time Considerations
Minimum on‑time t
that the LTC3729 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on‑time
limit and care should be taken to ensure that:
If the duty cycle falls below what can be accommodated
by the minimum on‑time, the LTC3729 will begin to skip
cycles resulting in nonconstant frequency operation. The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
The minimum on‑time for the LTC3729 is approximately
100ns. However, as the peak sense voltage decreases
the minimum on‑time gradually increases. This is of
particular concern in forced continuous applications with
low ripple current at light loads. If the duty cycle drops
below the minimum on‑time limit in this situation, a
significant amount of cycle skipping can occur with cor‑
respondingly larger current and voltage ripple.
If an application can operate close to the minimum on‑time
limit, an inductor must be chosen that has a low enough
inductance to provide sufficient ripple amplitude to meet
the minimum on‑time requirement. As a general rule,
keep the inductor ripple current of each phase equal to or
greater than 15% of I
t
ON MIN
(
LP
and R
)
<
V
V
IN
OUT
LP
LP
( )
f
determine how fast the loop acquires
=10k and C
ON(MIN)
OUT(MAX)
is the smallest time duration
LP
/N at V
LP
, R
is 0.01µF to 0.1µF .
LP
) smooth out the cur‑
IN(MAX)
LTC3729
.
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