LTC3729EG#TR Linear Technology, LTC3729EG#TR Datasheet - Page 18

• Manufacturer Part Number: LTC3729EG#TR
• Description: IC SW REG SYNC STEP-DOWN 28-SSOP
• Manufacturer: Linear Technology
• Series: PolyPhase®r
• Type: Step-Down (Buck)r

Specifications of LTC3729EG#TR

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.8 ~ 5 V
• Current - Output: 5A
• Frequency - Switching: 1.1MHz
• Voltage - Input: 4 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Other names: LTC3729EGTR

APPLICATIONS INFORMATION
LTC3729
pulled all the way to ground there is a delay before starting
of approximately:
The time for the output current to ramp up is then:
By pulling the RUN/SS pin below 0.8V the LTC3729 is
put into low current shutdown (I
be driven directly from logic as shown in Figure 6. Diode
D1 in Figure 6 reduces the start delay but allows C
ramp up slowly providing the soft‑start function. The
RUN/SS pin has an internal 6V zener clamp (see Functional
Diagram).
Fault Conditions: Overcurrent Latchoff
The RUN/SS pin also provides the ability to latch off the
controllers when an overcurrent condition is detected.
The RUN/SS capacitor, C
inrush current of both controllers. After the controllers
have been started and been given adequate time to charge
up the output capacitors and provide full load current, the
RUN/SS capacitor is used for a short‑circuit timer. If the
output voltage falls to less than 70% of its nominal value
after C
sumption that the output is in an overcurrent condition. If
the condition lasts for a long enough period as determined
by the size of C
the RUN/SS pin voltage is recycled. If the overload occurs
during start‑up, the time can be approximated by:
If the overload occurs after start‑up, the voltage on C
will continue charging and will provide additional time
before latching off:
This built‑in overcurrent latchoff can be overridden by
providing a pull‑up resistor, R
shown in Figure 6. This resistance shortens the soft‑
start period and prevents the discharge of the RUN/SS
capacitor during a severe overcurrent and/or short‑circuit
18
t
t
t
t
LO1
LO2
DELAY
RAMP
SS
≈ (C
≈ (C
reaches 4.1V, C
=
=
SS
SS
3V − 1.5V
1.2µA
1.5V
1.2µA
• 0.6V)/(1.2µA) = 5 • 10
• 3V)/(1.2µA) = 2.5 • 10
SS
, the controller will be shut down until
C
SS
C
= 1.25s / µF
SS
SS
SS
(
= 1.25s / µF
begins discharging on the as‑
, is used initially to limit the
(
SS
Q
, to the RUN/SS pin as
< 40µA). RUN/SS can
)
C
5
6
SS
)
(C
(C
C
SS
SS
SS
)
)
SS
SS
to
condition. When deriving the 5µA current from V
in the figure, current latchoff is always defeated. Diode‑
connecting this pull‑up resistor to INTV
eliminates any extra supply current during shutdown
while eliminating the INTV
controller start‑up.
Why should you defeat current latchoff? During the pro‑
totyping stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
short‑circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. A decision can be made after the design is com‑
plete whether to rely solely on foldback current limiting
or to enable the latchoff feature by removing the pull‑up
resistor.
The value of the soft‑start capacitor C
be scaled with output voltage, output capacitance and
load current characteristics. The minimum soft‑start
capacitance is given by:
The minimum recommended soft‑start capacitor of C
0.1µF will be sufficient for most applications.
Phase-Locked Loop and Frequency Synchronization
The LTC3729 has a phase‑locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn‑on to be locked to the
rising edge of an external source. The frequency range
of the voltage controlled oscillator is ±50% around the
center frequency f
pin of 1.2V corresponds to a frequency of approximately
C
3.3V OR 5V
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
SS
> (C
OUT
D1
Figure 6. RUN/SS Pin Interfacing
)(V
V
IN
R
OUT
O
SS
. A voltage applied to the PLLFLTR
*
RUN/SS
)(10
C
‑4
SS
CC
)(R
SENSE
loading from preventing
D1*
)
INTV
CC
SS
CC
R
, as in Figure 6,
SS
*
may need to
RUN/SS
3729
C
SS
F06
IN
3729fb
SS
as
=