XR16L784IV-F Exar Corporation, XR16L784IV-F Datasheet - Page 33

• Manufacturer Part Number: XR16L784IV-F
• Description: IC UART 8B 3.3V QUAD 64LQFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR16L784IV-F

• Number Of Channels: 4, QUART
• Package / Case: 64-LQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 4
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1282

REV. 1.2.3
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
•
•
The MCR register is used for controlling the modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin may be used for automatic hardware flow control enabled by EFR bit-6 and MCR bit-2=1. If the
modem interface is not used, this output may be used for general purpose.
•
•
MCR[1]: RTS# Output
The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit-6 and MCR bit-2=0. If
the modem interface is not used, this output may be used for general purpose.
•
•
MCR[2]: RTS/CTS or DTR/DSR for Auto Flow Control
DTR# or RTS# auto hardware flow control select. This bit is in effect only when auto RTS/DTR is enabled by
EFR bit-6.
•
•
MCR[3]: Reserved
MCR[4]: Internal Loopback Enable
•
•
MCR[5]: Xon-Any Enable
•
•
MCR[6]: Infrared Encoder/Decoder Enable
The state of this bit depends on the sampled logic level of pin ENIR during power up, following a hardware
reset (rising edge of RST# input). Afterward user can override this bit for desired operation.
•
•
MCR[7]: Clock Prescaler Select
•
•
4.7
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
Logic 0 = Force DTR# output to a logic 1 (default).
Logic 1 = Force DTR# output to a logic 0.
Logic 0 = Force RTS# output to a logic 1 (default).
Logic 1 = Force RTS# output to a logic 0.
Logic 0 = RTS# (RX side) and CTS# (TX side) pins are used for auto hardware flow control (default).
Logic 1 = DTR# (RX side) and DSR# (TX side) pins are used for auto hardware flow control.
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and
Logic 0 = Disable Xon-Any function (default).
Logic 1 = Enable Xon-Any function. In this mode any RX character received will enable Xon, resume data
transmission.
Logic 0 = Enable the standard modem receive and transmit character interface.
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/
input are routed to the infrared encoder/decoder. The data input and output levels will conform to the IrDA
infrared interface requirement. As such, while in this mode the infrared TX output will be a logic 0 during idle
data conditions. FCTR bit-4 may be selected to invert the RX input signal level going to the decoder for
infrared modules that provide rather an inverted output.
Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
Modem Control Register (MCR) - Read/Write
33
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
Figure 12
.
XR16L784