MC9328MXLCVP15R2 Freescale Semiconductor, MC9328MXLCVP15R2 Datasheet - Page 67

no-image

MC9328MXLCVP15R2

Manufacturer Part Number
MC9328MXLCVP15R2
Description
IC MCU I.MXL 150MHZ 225-MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MXLr
Datasheet

Specifications of MC9328MXLCVP15R2

Core Processor
ARM9
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, I²C, Memory Stick, MMC/SD, SPI, SSI, UART/USART, USB
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
97
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
1.7 V ~ 3.3 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
225-MAPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9328MXLCVP15R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
4.9
The PWM can be programmed to select one of two clock signals as its source frequency. The selected
clock signal is passed through a divider and a prescaler before being input to the counter. The output is
available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in
Figure 51
Freescale Semiconductor
1
2
3
4
Ref No.
Ref
No.
Loading capacitor condition is less than or equal to 30pF.
An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the MS_SDIO pin,
because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick SDIO pin when the pin
direction changes.
If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge.
If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge.
12
13
14
15
16
2a
2b
3a
1
Pulse-Width Modulator
and the parameters are listed in
MS_SDIO output delay time
MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0)
MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)
MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1)
MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)
System CLK frequency
Clock high time
Clock low time
Clock fall time
System Clock
PWM Output
Parameter
Table 25. MSHC Signal Timing Parameter Table (Continued)
1
1
1
Table 26. PWM Output Timing Parameter Table
1
Figure 51. PWM Output Timing Diagram
1,2
Parameter
MC9328MXL Technical Data, Rev. 8
Minimum
2a
Table
3.3
7.5
0
4a
26.
1.8 ± 0.1 V
2b
Maximum
87
5
Functional Description and Application Information
1
3a
3
4
3
4
Minimum
5/10
5/10
Minimum
0
18
23
3.0 ± 0.3 V
0
0
3.0 ± 0.3 V
3b
4b
Maximum
Maximum
5/10
100
3
Unit
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
67

Related parts for MC9328MXLCVP15R2