MC9S08RD32DWER Freescale Semiconductor, MC9S08RD32DWER Datasheet - Page 183
MC9S08RD32DWER
Manufacturer Part Number
MC9S08RD32DWER
Description
IC MCU 8BIT 32K FLASH 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08RE8FJE.pdf
(234 pages)
Specifications of MC9S08RD32DWER
Core Processor
HCS08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (0.300", 7.50mm Width)
Processor Series
S08RD
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI1, SPI1
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
39
Number Of Timers
2
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08RG60E
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
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Chapter 15
Development Support
15.1
15.1.1
Features of the background debug controller (BDC) include:
Features of the debug module (DBG) include:
Freescale Semiconductor
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Single pin for mode selection and background communications
BDC registers are not located in the memory map
SYNC command to determine target communications rate
Non-intrusive commands for memory access
Active background mode commands for CPU register access
GO and TRACE1 commands
BACKGROUND command can wake CPU from stop or wait modes
One hardware address breakpoint built into BDC
Oscillator runs in stop mode, if BDC enabled
COP watchdog disabled while in active background mode
Two trigger comparators:
— Two address + read/write (R/W) or
— One full address + data + R/W
Flexible 8-word by 16-bit FIFO (first-in, first-out) buffer for capture information:
— Change-of-flow addresses or
— Event-only data
Two types of breakpoints:
— Tag breakpoints for instruction opcodes
— Force breakpoints for any address access
Nine trigger modes:
— A-only
— A OR B
— A then B
— A AND B data (full mode)
— A AND NOT B data (full mode)
— Event-only B (store data)
— A then event-only B (store data)
Introduction
Features
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
183
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