LPC1102UK,118 NXP Semiconductors, LPC1102UK,118 Datasheet

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LPC1102 32-bit ARM Cortex-M0 microcontroller flash and 8 kB SRAM Rev. 2 — 26 November 2010 1. General description The LPC1102 is an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, ...

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... NXP Semiconductors Serial interfaces: UART with fractional baud rate generation, internal FIFO, and RS-485 support. One SPI controller with SSP features and with FIFO and multi-protocol capabilities (see Clock generation: 12 MHz internal RC oscillator trimmed accuracy that can optionally be used as a system clock. ...

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... NXP Semiconductors 4.1 Ordering options Table 2. Type number LPC1102UK 5. Block diagram LPC1102 HIGH-SPEED GPIO port GPIO PIO0/1 RXD TXD CT32B0_MAT[3,1,0] 32-bit COUNTER/TIMER 0 CT32B1_MAT[2:0] 32-bit COUNTER/TIMER 1 CT32B1_CAP0 CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 16-bit COUNTER/TIMER 1 Fig 1. LPC1102 block diagram LPC1102 Preliminary data sheet Ordering options ...

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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. 6.2 Pin description Table 3. LPC1102 pin description table Symbol Pin [2][3] RESET/PIO0_0 C1 [4] PIO0_8/MISO/ A2 CT16B0_MAT0 [4] PIO0_9/MOSI/ A3 CT16B0_MAT1 [4] SWCLK/ A4 PIO0_10/ SCK/CT16B0_MAT2 [5] R/PIO0_11/ B4 AD0/CT32B0_MAT3 LPC1102 Preliminary data sheet ball A1 index area Pin configuration WLCSP16 package Start ...

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... NXP Semiconductors Table 3. LPC1102 pin description table Symbol Pin [5] R/PIO1_0/ B3 AD1/CT32B1_CAP0 [5] R/PIO1_1/ C4 AD2/CT32B1_MAT0 [5] R/PIO1_2/ C3 AD3/CT32B1_MAT1 [5] SWDIO/PIO1_3/AD4/ D4 CT32B1_MAT2 [4] PIO1_6/RXD/ C2 CT32B0_MAT0 [4] PIO1_7/TXD/ D1 CT32B0_MAT1 V D2 [6] XTALIN [1] Pin state at reset for default function Input internal pull-up enabled. [2] See Figure 20 for the reset pad configuration. ...

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... NXP Semiconductors 7. Functional description 7.1 ARM Cortex-M0 processor The ARM Cortex- general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 On-chip flash program memory The LPC1102 contains on-chip flash memory. Remark: The LPC1102 supports In-Application Programming (IAP) and In-System Programming (ISP) ...

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... NXP Semiconductors LPC1102 4 GB reserved private peripheral bus reserved AHB peripherals reserved APB peripherals 1 GB reserved 0.5 GB reserved 16 kB boot ROM reserved 8 kB SRAM reserved 32 kB on-chip flash 0 GB Fig 3. LPC1102 memory map 7.5 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts ...

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... NXP Semiconductors • Four programmable interrupt priority levels, with hardware priority level masking. • Software interrupt generation. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source ...

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... NXP Semiconductors The UART includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.8.1 Features • Maximum UART data bit rate of 3.125 Mbit/s. • 16 Byte Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. ...

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... NXP Semiconductors • Measurement range 10-bit conversion time ≥ 2.44 μs. • • Burst conversion mode for single or multiple inputs. • Optional conversion on transition of input pin or timer match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. 7.11 General purpose external event counter/timers The LPC1102 includes two 32-bit counter/timers and two 16-bit counter/timers ...

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... NXP Semiconductors • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 24-bit timer with internal prescaler. • Selectable time period from (T multiples of T • The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator (IRC), the Watchdog oscillator, or the main clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions ...

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... NXP Semiconductors IRC oscillator watchdog oscillator IRC oscillator external clock SYSPLLCLKSEL (system PLL clock select) Fig 4. LPC1102 clock generation block diagram 7.14.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed accuracy over the entire voltage and temperature range ...

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... NXP Semiconductors following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 μs. 7.14.3 Wake-up process The LPC1102 begins operation at power-up by using the 12 MHz IRC oscillator as the clock source ...

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... NXP Semiconductors Six of the GPIO pins (see logic to wake up the chip from Deep-sleep mode. The clock source should be switched to IRC before entering Deep-sleep mode unless the watchdog oscillator remains running in Deep-sleep mode. The IRC can be switched on and off glitch-free and provides a clean clock signal after start-up. ...

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... NXP Semiconductors 3. Running an application with level CRP3 selected fully disables any access to the chip via the SWD pins. Remark: The LPC1102 does not provide an ISP entry pin to be monitored at reset. For all three CRP levels, the user’s application code must provide a flash update mechanism which reinvokes ISP by defining a user-selected PIO pin for ISP entry ...

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... NXP Semiconductors 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (core and external rail input voltage I I supply current DD I ground current SS I I/O latch-up current latch T storage temperature stg T maximum junction temperature ...

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... NXP Semiconductors 9. Static characteristics Table 5. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter V supply voltage (core DD and external rail) I supply current DD Standard port pins, RESET I LOW-level input current HIGH-level input IH current I OFF-state output OZ current V input voltage I V output voltage ...

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... NXP Semiconductors Table 5. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter I LOW-level output OL current I HIGH-level short-circuit OHS output current I LOW-level short-circuit OLS output current I pull-down current pd I pull-up current pu External clock input V crystal input voltage i(xtal) Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. ...

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... NXP Semiconductors Table 6. ADC static characteristics − ° ° +85 C unless otherwise specified; ADC frequency 4.5 MHz, V amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G E absolute error ...

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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 5. ADC characteristics LPC1102 Preliminary data sheet ...

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... NXP Semiconductors 9.1 BOD static characteristics Table amb Symbol V th [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC111x user manual. 9.2 Power consumption Power measurements in Active, Sleep, and Deep-sleep modes were performed under the following conditions (see LPC111x user manual): • ...

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... NXP Semiconductors (1) System PLL disabled; IRC enabled. (2) System PLL enabled; IRC disabled. Fig 6. (1) System PLL disabled; IRC enabled. (2) System PLL enabled; IRC disabled. Fig 7. LPC1102 Preliminary data sheet <tbd> °C; active mode entered executing code Conditions: T amb peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral clocks disabled ...

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... NXP Semiconductors (1) System PLL disabled; IRC enabled. (2) System PLL enabled; IRC disabled. Fig 8. Fig 9. LPC1102 Preliminary data sheet <tbd> Conditions 3.3 V; sleep mode entered from flash; all peripherals disabled in the DD SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled. ...

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... NXP Semiconductors 9.3 Electrical pin characteristics (mA) Fig 10. Typical LOW-level output current I V Fig 11. Typical HIGH-level output voltage V LPC1102 Preliminary data sheet 0.2 Conditions 3.3 V; standard port pins. DD 3 °C 25 °C 3.2 −40 °C 2.8 2 Conditions 3.3 V; standard port pins All information provided in this document is subject to legal disclaimers. ...

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... NXP Semiconductors (μA) Fig 12. Typical pull-up current I (μA) Fig 13. Typical pull-down current I LPC1102 Preliminary data sheet −10 − °C 25 °C −40 °C −50 − Conditions 3.3 V; standard port pins. DD versus input voltage ° °C −40 ° Conditions 3.3 V; standard port pins. ...

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... NXP Semiconductors 10. Dynamic characteristics 10.1 Flash memory Table 8. − amb Symbol N endu t ret prog [1] Number of program/erase cycles. [2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes. 10.2 External clock Table 9. ...

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... NXP Semiconductors 10.3 Internal oscillators Table 10. − amb Symbol f osc(RC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply [2] voltages. Fig 15. Internal RC oscillator frequency versus temperature Table 11 ...

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... NXP Semiconductors 10.4 I/O pins Table 12. − amb Symbol [1] Applies to standard port pins and RESET pin. 10.5 SPI interfaces Table 13. Dynamic characteristics of SPI pins in SPI mode Symbol Parameter SPI master (in SPI mode) T clock cycle time cy(clk) t data set-up time DS t data hold time ...

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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 16. SPI master timing in SPI mode LPC1102 Preliminary data sheet T cy(clk) t v(Q) DATA VALID MOSI MISO DATA VALID t v(Q) DATA VALID MOSI t DATA VALID MISO All information provided in this document is subject to legal disclaimers. Rev. 2 — 26 November 2010 ...

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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 17. SPI slave timing in SPI mode LPC1102 Preliminary data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t MOSI DATA VALID t v(Q) MISO DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 2 — 26 November 2010 ...

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... NXP Semiconductors 11. Application information 11.1 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in • The ADC input trace must be short and as close as possible to the LPC1102 chip. • The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines. • ...

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... NXP Semiconductors pin configured as digital output pin configured as digital input pin configured as analog input Fig 19. Standard I/O pad configuration 11.4 Reset pad configuration Fig 20. Reset pad configuration LPC1102 Preliminary data sheet output enable output driver repeater mode enable data input analog input ...

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... NXP Semiconductors 12. Package outline WLCSP16: wafer level chip-size package; 16 bumps; body 2.17 x 2.32 x 0.6 mm ball A1 index area ball A1 1 index area Dimensions Unit max 0.65 0.27 0.38 0.35 mm nom 0.60 0.24 0.36 0.32 min 0.55 0.21 0.34 0.29 Outline version IEC ...

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... NXP Semiconductors 13. Abbreviations Table 14. Acronym ADC AHB APB BOD GPIO PLL RC SPI SSI SSP UART LPC1102 Preliminary data sheet Abbreviations Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Peripheral Bus BrownOut Detection General Purpose Input/Output Phase-Locked Loop Resistor-Capacitor Serial Peripheral Interface Serial Synchronous Interface ...

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... NXP Semiconductors 14. Revision history Table 15. Revision history Document ID Release date LPC1102 v.2 20101126 Modifications: LPC1102 v.1 20101116 LPC1102 Preliminary data sheet Data sheet status Preliminary data sheet - • Changed data sheet status to Preliminary. Objective data sheet All information provided in this document is subject to legal disclaimers. ...

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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

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... Preliminary data sheet NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 ARM Cortex-M0 processor . . . . . . . . . . . . . . . . 6 7.2 On-chip flash program memory . . . . . . . . . . . . 6 7.3 On-chip SRAM ...