CM1293A-02SR ON Semiconductor, CM1293A-02SR Datasheet - Page 7

• Manufacturer Part Number: CM1293A-02SR
• Description: ESD PROT LOW CAP 2CH 143SOT-4
• Manufacturer: ON Semiconductor

Specifications of CM1293A-02SR

• Voltage - Reverse Standoff (typ): 3.3V
• Voltage - Breakdown: 6V
• Power (watts): 225mW
• Polarization: 2 Channel Array - Bidirectional
• Mounting Type: Surface Mount
• Package / Case: SOT-143-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CM1293A
Application Information
Design Considerations
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to
minimize parasitic series inductances on the Supply/Ground rails as well as the signal trace segment between
the signal input (typically a connector) and the ESD protection device. Refer to
example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power
supply is represented by L
where I
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact
discharge per the IEC61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1ns.
Here d(I
combined) will lead to a 300V increment in V
Similarly for negative ESD pulses, parasitic series inductance from the V
drastically increased negative voltage on the line being protected.
The CM1293 has an integrated Zener diode between V
inductance L
possible V
recommended that a 0.22µF ceramic chip capacitor be connected between V
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of
expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to
the V
planes and between the signal input and the ESD device to minimize stray series inductance.
V
CL
P
= Fwd voltage drop of D
pin of the Protection Array as possible, with minimum PCB trace lengths to the power supply, ground
ESD
ESD
is the ESD current pulse, and V
CL
)/dt can be approximated by ∆I
, especially when V
Figure 3. Application of Positive ESD Pulse between Input Channel and Ground
2
on V
CL
by clamping V
1
1
and L
+ V
SUPPLY
P
2
. The voltage V
is biased at a voltage significantly below the Zener breakdown voltage, it is
+ L
P
1
x d(I
at the breakdown voltage of the Zener diode. However, for the lowest
Rev. 4 | Page 7 of 16 | www.onsemi.com
SUPPLY
ESD
ESD
)
CL
/
/∆t, or 30/(1x10
dt+ L
!
is the positive supply voltage.
CL
2
on the line being protected is:
x d(I
ESD
P
)
/
and V
dt
-9
). So just 10nH of series inductance (L
N
. This greatly reduces the effect of supply rail
N
pin to the ground rail will lead to
P
and the ground plane.
Figure
3, which illustrates an
1
and L
2