MAX16048ACB+ Maxim Integrated Products, MAX16048ACB+ Datasheet - Page 46

• Manufacturer Part Number: MAX16048ACB+
• Description: IC EE-PROG SYS MGR 8CH 64-TQFP
• Manufacturer: Maxim Integrated Products
• Type: System Managerr

Specifications of MAX16048ACB+

• Number Of Voltages Monitored: 8
• Output: Open Drain, Push-Pull
• Reset: Active Low
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: Adjustable/Selectable
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The watchdog timer can operate together with or inde-
pendently of the MAX16046A/MAX16048A. When oper-
ating in dependent mode, the watchdog is not
activated until the sequencing is complete and RESET
is de-asserted. When operating in independent mode,
the watchdog timer is independent of the sequencing
operation and activates immediately after V
the UVLO threshold and the boot phase is complete.
Set r4Dh[3] to ‘0’ to configure the watchdog in depen-
dent mode. Set r4Dh[3] to ‘1’ to configure the watchdog
in independent mode. See Table 28 for more informa-
tion on configuring the watchdog timer in dependent or
independent mode.
The watchdog timer can be used to monitor µP activity
in two modes. Flexible timeout architecture provides an
adjustable watchdog startup delay of up to 192s, allow-
ing complicated systems to complete lengthy boot-up
routines. An adjustable watchdog timeout allows the
supervisor to provide quick alerts when processor
activity fails. After each reset event (V
UVLO then returns above UVLO, software reboot, man-
ual reset (MR), EN input going low then high, or watch-
dog reset) and once sequencing is complete, the
watchdog startup delay provides an extended time for
the system to power up and fully initialize all µP and
system components before assuming responsibility for
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
Table 27. RESET Configuration and Dependencies (continued)
* MAX16046A only
46
REGISTER/
ADDRESS
______________________________________________________________________________________
EEPROM
1Ah
1Bh
Dependent Watchdog Timer Operation
BIT RANGE
[7:4]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
RESET DEPENDENCIES
1 =
1 =
1 =
1 =
1 =
1 =
1 =
1 =
1 =
1 =
1 =
1 =
Reserved
Watchdog Timer
CC
drops below
is dependent on MON1
is dependent on MON2
is dependent on MON3
is dependent on MON4
is dependent on MON5
is dependent on MON6
is dependent on MON7
is dependent on MON8
is dependent on MON9*
is dependent on MON10*
is dependent on MON11*
is dependent on MON12*
CC
exceeds
routine watchdog updates. Set r55h[6] to ‘1’ to enable
the watchdog startup delay. Set r55h[6] to ‘0’ to disable
the watchdog startup delay.
The normal watchdog timeout period, t
the first transition on WDI before the conclusion of the
long startup watchdog period, t
and 7). During the normal operating mode, WDO
asserts if the µP does not toggle WDI with a valid transi-
tion (high-to-low or low-to-high) within the standard
timeout period, t
is toggled or RESET is asserted (Figure 7).
While EN is low, or r55h[7] is a ‘0,’ the watchdog timer is
in reset. The watchdog timer does not begin counting until
the power-on mode is reached and RESET is deasserted.
The watchdog timer is reset and WDO deasserts any time
RESET is asserted (Figure 8). The watchdog timer will be
held in reset while RESET is asserted.
The watchdog can be configured to control the RESET
output as well as the WDO output. RESET is pulsed low
for the reset timeout, t
expires and the Watchdog Reset Output Enable bit
(r55h[7]) is set to ‘1.’ Therefore, WDO pulses low for a
short time (approximately 1µs) when the watchdog timer
expires. RESET is not affected by the watchdog timer
when the Watchdog Reset Output Enable bit (r55h[7]) is
set to ‘0.’
See Table 29 for more information on configuring
watchdog functionality.
DESCRIPTION
WDI
. WDO remains asserted until WDI
RP
, when the watchdog timer
WDI_STARTUP
WDI
, begins after
(Figures 6