MAX817LCSA+T Maxim Integrated Products, MAX817LCSA+T Datasheet - Page 7

• Manufacturer Part Number: MAX817LCSA+T
• Description: IC SUPERVISOR MPU 5V 8-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Battery Backup Circuitr

Specifications of MAX817LCSA+T

• Number Of Voltages Monitored: 1
• Reset: Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 4.65V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output: -

______________________________________________________________Pin Description
MAX817
—
—
—
1
2
3
4
5
6
7
8
MAX818
PIN
—
—
—
1
2
3
4
5
6
7
8
+5V Microprocessor Supervisory Circuits
_______________________________________________________________________________________
MAX819
—
—
—
1
2
3
4
5
6
7
8
CE OUT
RESET
NAME
CE IN
BATT
GND
OUT
V
PFO
WDI
PFI
MR
CC
Supply Output for CMOS RAM. When V
or above V
MOSFET switch. When V
Input Supply Voltage, +5V input.
Ground. 0V reference for all signals.
Power-Fail Comparator Input. When V
V
section). Connect to ground if unused.
Chip-Enable Input. The input to the chip-enable gating circuit. Connect to
ground if unused.
Power-Fail Comparator Output. When PFI is less than V
below V
enable the battery freshness seal (see Battery Freshness Seal and Power-Fail
Comparator sections).
Chip-Enable Output. CE OUT goes low only if CE IN is low while reset is not
asserted. If CE IN is low when reset is asserted, CE OUT will remain low for
15µs or until CE IN goes high, whichever occurs first. CE OUT is pulled up to
OUT in battery-backup mode. CE OUT is also used to enable the battery
freshness seal (see Battery Freshness Seal section).
Watchdog Input. If WDI remains either high or low for longer than the watch-
dog timeout period, the internal watchdog timer runs out and a reset is trig-
gered. If WDI is left unconnected or is connected to a high-impedance
three-state buffer, the watchdog feature is disabled. The internal watchdog
timer clears whenever reset is asserted, WDI is three-stated, or WDI sees a ris-
ing or falling edge. The WDI input is designed to be driven by a three-stated-
output device with a maximum high-impedance leakage current of 10µA and a
maximum output capacitance of 200pF. The output device must also be capa-
ble of sinking and sourcing 200µA when active.
Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted
for as long as MR is held low and for 200ms after MR returns high. The active-
low input has an internal 63k pull-up resistor. It can be driven from a TTL- or
CMOS-logic line or shorted to ground with a switch. Leave open, or connect to
V
Active-Low Reset Output. Pulses low for 200ms when triggered and remains
low whenever V
remains low for 200ms after V
triggers a reset, or MR goes low to high.
Backup-Battery Input. When V
BATT. When V
BATT
CC
if unused.
, PFO goes low; otherwise, PFO remains high (see Power-Fail Comparator
BATT
BATT
, PFO goes low; otherwise PFO remains high. PFO is also used to
CC
, OUT is connected to V
CC
rises above V
is below the reset threshold or when MR is a logic low. It
CC
falls below V
CC
CC
BATT
FUNCTION
rises above the reset threshold, the watchdog
falls below V
, OUT reconnects to V
PFI
CC
CC
is below V
BATT
rises above the reset threshold
through an internal P-channel
, BATT connects to OUT.
BATT
PFT
, OUT switches from V
or when V
PFT
CC
or when V
.
CC
is below
CC
is
CC
to
7