X40020S14Z-B Intersil, X40020S14Z-B Datasheet - Page 7

• Manufacturer Part Number: X40020S14Z-B
• Description: IC VOLTAGE MONITOR DUAL 14-SOIC
• Manufacturer: Intersil
• Type: Multi-Voltage Supervisorr

Specifications of X40020S14Z-B

• Number Of Voltages Monitored: 2
• Output: Open Drain or Open Collector
• Reset: Active High
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 2.6V, 4.6V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Resetting the V
To reset a V
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V
Byte in order to reset V
valid
sequence. Pin WDO must then be brought LOW to
complete the operation.
After being reset, the value of V
value of 1.7V or lesser.
Note: This operation does not corrupt the registers.
System Battery Switch
As long as V
old V
cal) switch. When the V
then V
greater than V
than V
through an 80Ω (typical) switch. V
the system static RAM voltage, so the switchover circuit
operates to protect the contents of the static RAM dur-
ing a power failure. Typically, when V
SRAMs go into a lower power state and draw much less
current than in their active mode. When V
V
0.03V. There is a 60mV hysteresis around this battery
switch threshold to prevent oscillations between sup-
plies.
While V
pulled LOW. The signal can drive an external PNP tran-
sistor to provide additional current to the external circuits
during normal operation.
Operation
The device is in normal operation with V
V
when V
Figure 5. Sample V
TRIP1
OUT
CC
V
Adj.
> V
TRIP1
TRIP
switches back to V
CC
BATT
write
and 0Bh for V
CC
CC
TRIP1
, V
is applied to V
goes away.
is connected to V
OUT
- 0.03V, then V
TRIPx
CC
. It switches to the battery backup mode
operation
BATT
TRIPx
exceeds the low voltage detect thresh-
is connected to V
voltage, apply the programming volt-
- 0.03V. When V
TRIP
TRIP2
V
Voltage
Adj.
TRIP2
TRIPx
CC
Reset Circuit
CC
OUT
, followed by 00h for the Data
initiates
7
OUT
when V
. The STOP bit following a
has fallen below V1
OUT
TRIPx
if V
is connected to V
CC
OUT
CC
the BATT-ON pin is
V2FAIL
RESET
CC
4.7K
becomes a nominal
the
through a 5Ω (typi-
CC
is or equal to or
CC
typically supplies
exceeds V
has failed, the
CC
drops to less
programming
CC
as long as
returns,
BATT
X40020, 40021
TRIP
BATT
+
1
6
2
7
,
X40020
Control Register
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings.
The Block Lock and Watchdog Timer bits are nonvolatile
and do not change when power is removed.
The Control Register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte write
operation directly to the address of the register and only
one data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Registers" on page 8.
The user must issue a stop, after sending this byte to the
register, to initiate the nonvolatile cycle that stores WD1,
WD0, PUP1, and PUP0. The X40020 will not acknowl-
edge any data bytes written after the first byte is entered.
The state of the Control Register can be read at any time
by performing a random read at address 01Fh, using the
special preamble. Only one byte is read by each register
read operation. The master should supply a stop condi-
tion to be consistent with the bus protocol, but a stop is
not required to end this operation.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
13
14
PUP1 WD1 WD0
9
8
V
V
V
0 ≤ V
and V
CC
CC
BATT
7
Condition
> V
> V
CC
CC
= 0
TRIP1
TRIP1
≤ V
6
< V
TRIP1
BATT
&
5
Adjust
Run
Normal Operation
Normal Operation without battery
backup capability
Battery Backup mode; RESET
signal is asserted. No communica-
tion to the device is allowed.
4
0
V
P
Mode of Operation
3
0
SCL
SDA
RWEL WEL PUP0
2
µC
1
May 17, 2006
FN8112.1
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