STM6822SWY6F STMicroelectronics, STM6822SWY6F Datasheet - Page 11

• Manufacturer Part Number: STM6822SWY6F
• Description: IC SUPERVISOR PB 2.93V SOT23-5
• Manufacturer: STMicroelectronics
• Type: Simple Reset/Power-On Resetr

Specifications of STM6822SWY6F

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 2.93V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-5, SC-74A, SOT-25
• Number Of Elements: 1
• Monitored Voltage 1 (typ): 2.5/3/3.3/5V
• Threshold Voltage 1 (max): 2.96V
• Battery Backup Switching: No
• Watchdog Timer: Yes
• Chip Enable Signals: No
• Reset Active Time: 280ms
• Manual Reset: Yes
• Package Type: SOT-23
• Operating Supply Voltage (min): 1V
• Operating Supply Voltage (max): 5.5V
• Reset Threshold Voltage (max): 2.96V
• Reset Threshold Voltage (min): 2.89V
• Family Name: STM6822
• Power Dissipation: 320mW
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Power Fail Detection: No
• Mounting: Surface Mount
• Pin Count: 5
• Supply Current: 0.012mA
• Monitored Voltage: 2.5 V, 3 V, 3.3 V, 5 V
• Output Type: Active Low, Open Drain
• Watchdog: Watchdog
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1 V
• Supply Current (typ): 12 uA
• Maximum Power Dissipation: 320 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Undervoltage Threshold: 2.89 V
• Overvoltage Threshold: 2.96 V
• Power-up Reset Delay (typ): 280 ms
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4799-2

STM6321/6322STM6821/6822/6823/6824/6825
2.3
2.4
Note:
2.5
2.5.1
2.5.2
Push-button reset input (STM6322/6821/6822/6823/6825)
A logic low on MR asserts reset. Reset remains asserted while MR is low, and for t
Figure 25 on page
resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic
levels or with open drain/collector outputs. Connect a normally open momentary switch from
MR to GND to create a manual reset function; external debounce circuitry is not required. If
MR is driven from long cables or the device is used in a noisy environment, connect a 0.1 µF
capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to
V
Watchdog input (STM6321/6821/6822/6823/6824)
The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not
toggle the Watchdog Input (WDI) within t
watchdog timer is cleared by either:
1.
2.
The timer remains cleared and does not count for as long as reset is asserted. As soon as
reset is released, the timer starts counting.
The watchdog function may be disabled by floating WDI or tri-stating the driver connected to
WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and
the maximum allowable load capacitance is 200 pF.
Applications information
The WDI input is internally driven through a buffer and series resistor from the watchdog
counter. For minimum watchdog input current (minimum overall power consumption), leave
WDI low for the majority of the watchdog timeout period. When high, WDI can draw as much
as 160 µA. Pulsing WDI high at a low duty cycle will reduce the effect of the large input
current. When WDI is left unconnected, the watchdog timer is serviced within the watchdog
timeout period by a low-high-low pulse from the counter chain.
Ensuring a valid reset output down to V
The STM6xxx supervisors are guaranteed to operate properly down to V
applications that require valid reset levels down to V
outputs (push/pull only, see
outputs (push/pull only, see
while the reset output can no longer sink or source current. This scheme does not work with
the open drain outputs of the STM6321/6322/6822.
The resistor value used is not critical, but it must be large enough not to load the reset
output when V
Watchdog input current
CC
when not used.
a reset pulse, or
by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns.
CC
is above the reset threshold. For most applications, 100 kΩ is adequate.
19) after it returns high. The MR input has an internal 52 kΩ pull-up
Figure 12 on page
Figure 13 on page
Doc ID 11110 Rev 10
WD
(1.6 sec), the reset is asserted. The internal
12) and a pull-up resistor to active-high
12) will ensure that the reset line is valid
CC
CC
= 0, a pull-down resistor to active-low
= 0 V
CC
= 1 V. In
Operation
rec
(see
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