TDA9901TS/C3,118 NXP Semiconductors, TDA9901TS/C3,118 Datasheet
TDA9901TS/C3,118
Specifications of TDA9901TS/C3,118
TDA9901TS/C3-T
TDA9901TS/C3-T
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TDA9901TS/C3,118 Summary of contents
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TDA9901 Wideband differential digital controlled variable gain amplifier Rev. 04 — 14 August 2008 1. General description The TDA9901 is a wideband, low-noise amplifier with differential inputs and outputs. The TDA9901 incorporates an Automatic Gain Control (AGC) function with digital ...
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... NXP Semiconductors 4. Quick reference data Table V11 to V12 = 4. 5. DDA shorted together; T and T amb Symbol Parameter V DDA V DDD I DDA I DDD G min G max B 3dB P tot [1] Due to on-chip regulator behavior a warm-up time of 1 minute (typical) is recommended for optimal performance. 5. Ordering information Table 2. Ordering information ...
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... NXP Semiconductors 6. Block diagram CMVGA Fig 1. Block diagram TDA9901_4 Product data sheet Wideband differential digital controlled variable gain amplifi GRAY2 DDD TDA9901 6 IN INN 12, 5 REFERENCE GENERATOR 11 V DDA Rev. 04 — 14 August 2008 TDA9901 GRAY1 GRAY0 CLK CLKN V SSD DECODER ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. Pin configuration 7.2 Pin description Table 3. Symbol GRAY0 TE CLK CLKN CMVGA IN INN n.c. n.c. n.c. V DDA V SSA n.c. OUTN OUT CMADC V SSD TDA9901_4 Product data sheet Wideband differential digital controlled variable gain amplifier ...
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... NXP Semiconductors Table 3. Symbol V DDD GRAY2 GRAY1 8. Functional description The TDA9901 provides a digitally controlled variable gain function for high-frequency applications. The TDA9901 can be operated in two different modes, depending on the value at pin TE. When logic 1, the gain can be instantly controlled when the clock signal is HIGH (transparent mode). The gain is fi ...
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... NXP Semiconductors 11. Characteristics Table 6. Characteristics V = V11 to V12 = 4. 5. DDA +85 C; typical values measured at V amb [1] . Symbol Parameter Supplies V analog supply voltage DDA V digital supply voltage DDD V supply voltage difference DD I analog supply current DDA I digital supply current DDD P total power dissipation tot Variable gain amplifi ...
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... NXP Semiconductors Table 6. Characteristics …continued V = V11 to V12 = 4. 5. DDA +85 C; typical values measured at V amb [1] . Symbol Parameter V equivalent output noise n(o)(eq) voltage PSRR power supply rejection ratio CMRR common mode rejection ratio Analog inputs V maximum peak-to-peak i(p-p)(max) input voltage V common-mode input ...
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... NXP Semiconductors Table 6. Characteristics …continued V = V11 to V12 = 4. 5. DDA +85 C; typical values measured at V amb [1] . Symbol Parameter third harmonic level third harmonic level 3H variation with temperature Reference voltage output ADC: pin CMADC V reference voltage ref R output resistance reference output voltage o(ref) ...
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... When driving the CLKN input with the same signal, gain change takes place on the falling edge of the clock signal. NXP Semiconductors recommends decoupling of the CLKN or CLK input to V via a 100 nF capacitor. ...
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... NXP Semiconductors 12. Additional information relating to Table 7. State other CLK GRAY0 GRAY1 GRAY2 t su OUT and OUTN t PD Fig 3. Latched mode timing diagram TDA9901_4 Product data sheet Wideband differential digital controlled variable gain amplifier Table 6 Input coding Gray input data code ...
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... NXP Semiconductors Fig 4. Transparent mode timing diagram with CLK HIGH FILTER 100 sine wave generator (1) C1 and C2 represent the board line capacitance. They represent about 5 pF with the ADC1206S040/055/070 input capacitance. Special care has to be taken to minimize this load in order to have the best dynamic performance. ...
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... NXP Semiconductors 55 HD (dBc ( ( Typical condition (p-p) differential output Fig 6. Harmonic Distortion (HD function of frequency for minimum gain 55 HD (dBc ( ( Typical condition (p-p) differential output Fig 8. Harmonic Distortion (HD function of frequency for minimum gain plus 12 dB TDA9901_4 Product data sheet Wideband differential digital controlled variable gain amplifier ...
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... NXP Semiconductors (1) (2) Fig 10. Harmonic Distortion (HD function of frequency for minimum gain plus 24 dB TDA9901_4 Product data sheet Wideband differential digital controlled variable gain amplifi (dBc Typical condition (p-p) differential output Rev. 04 — 14 August 2008 TDA9901 014aaa473 (1) ( (MHz) © NXP B.V. 2008. All rights reserved. ...
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... NXP Semiconductors 13. Application information 13.1 Application diagrams 100 nF 100 (1) Single-ended clock signal can be applied if required. (2) R1 and R2 should be at least 680 . Fig 11. Application diagram 13.2 Recommended companion chip Table 8. Type number ADC1006S055 ADC1006S070 ADC1206S040 ADC1206S055 ADC1206S070 TDA9901_4 Product data sheet Wideband differential digital controlled variable gain amplifier ...
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... NXP Semiconductors 14. Package outline SSOP20: plastic shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.4 mm 1.5 0.25 0 1.2 Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION IEC SOT266-1 Fig 12 ...
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... NXP Semiconductors 15. Revision history Table 9. Revision history Document ID Release date TDA9901_4 20080814 • Modifications: Correction made to V • Corrections made to values of t TDA9901_3 20080611 TDA9901_2 19991008 TDA9901_N_1 19980415 TDA9901_4 Product data sheet Wideband differential digital controlled variable gain amplifier ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Functional description . . . . . . . . . . . . . . . . . . . 5 9 Limiting values Thermal characteristics Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 12 Additional information relating to 13 Application information ...