AD744KRZ Analog Devices Inc, AD744KRZ Datasheet - Page 7

IC OPAMP BIFET 13MHZ PREC 8SOIC

AD744KRZ

Manufacturer Part Number
AD744KRZ
Description
IC OPAMP BIFET 13MHZ PREC 8SOIC
Manufacturer
Analog Devices Inc
Datasheets

Specifications of AD744KRZ

Slew Rate
75 V/µs
Amplifier Type
J-FET
Number Of Circuits
1
-3db Bandwidth
13MHz
Current - Input Bias
30pA
Voltage - Input Offset
250µV
Current - Supply
3.5mA
Current - Output / Channel
25mA
Voltage - Supply, Single/dual (±)
±4.5 V ~ 18 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Op Amp Type
Precision
No. Of Amplifiers
1
Bandwidth
13MHz
Supply Voltage Range
± 4.5V To ± 18V
Amplifier Case Style
SOIC
No. Of Pins
8
Common Mode Rejection Ratio
88
Current, Input Bias
30 pA
Current, Input Offset
10 pA
Current, Output
25 mA
Harmonic Distortion
0.0003 %
Impedance, Thermal
42 °C/W
Package Type
SOIC-8
Power Dissipation
500 mW
Resistance, Input
3×10^12 Ohms
Temperature, Operating, Range
0 to +70 °C
Voltage, Input
±20 V (Differential), -11.5 to +14.5 V (Common-Mode)
Voltage, Noise
45 nV/sqrt Hz
Voltage, Offset
0.25 mV
Voltage, Output, High
+13.9 V
Voltage, Output, Low
-13.3 V
Voltage, Supply
±15 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Output Type
-
Gain Bandwidth Product
-
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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POWER SUPPLY BYPASSING
The power supply connections to the AD744 must maintain a
low impedance to ground over a bandwidth of 10 MHz or more.
This is especially important when driving a significant resistive
or capacitive load, since all current delivered to the load comes
from the power supplies. Multiple high quality bypass capacitors
are recommended for each power supply line in any critical
application. A 0.1 µF ceramic and a 1 µF electrolytic capacitor
as shown in Figure 24 placed as close as possible to the ampli-
fier (with short lead lengths to power supply common) will
assure adequate high frequency bypassing, in most applica-
tions. A minimum bypass capacitance of 0.1 µF should be used
for any application.
MEASURING AD744 SETTLING TIME
The photos of Figures 26 and 27 show the dynamic response of
the AD744 while operating in the settling time test circuit of
Figure 25. The input of the settling time fixture is driven by a
flat-top pulse generator. The error signal output from the false
summing node of A1, the AD744 under test, is clamped, ampli-
fied by op amp A2 and then clamped again.
HP2835
+15V
COM
–15V
GENERATOR
EQUIVALENT
FLAT-TOP
DYNAMICS
PULSE
2X
DATA
5109
OR
+V
–V
S
S
0.47 F
1.1k
NOTE: USE CIRCUIT BOARD WITH GROUND PLANE
1 F
V
IN
AD3554
AD744
A2
10k
–V
4.99k
S
0.1 F
+V
–V
+V
5pF
S
S
S
10k
0.2pF – 0.8pF
5pF – 18pF
NULL
200
0.47 F
–V
1 F
A1
TO
TEKTRONIX
7A26
OSCILLOSCOPE
PREAMP
INPUT SECTION
(VIA LESS THAN 1 FT 50
COAXIAL CABLE)
1 F
S
+V
AD744
4.99k
10k
S
206
0.1 F
1 F
0.1 F
5k
2X
HP2835
V
0.1 F
1M
ERROR
10pF
10
20pF
The error signal is thus clamped twice: once to prevent overloading
amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. A Tektronix oscilloscope preamp type
7A26 was carefully chosen because it recovers from the
approximately 0.4 V overload quickly enough to allow accurate
measurement of the AD744’s 500 ns settling time. Amplifier A2
is a very high-speed FET-input op amp; it provides a voltage
gain of 10, amplifying the error signal output of the AD744
under test.
AD744

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