AD744KRZ Analog Devices Inc, AD744KRZ Datasheet - Page 12

• Manufacturer Part Number: AD744KRZ
• Description: IC OPAMP BIFET 13MHZ PREC 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD744KRZ

• Slew Rate: 75 V/µs
• Amplifier Type: J-FET
• Number Of Circuits: 1
• -3db Bandwidth: 13MHz
• Current - Input Bias: 30pA
• Voltage - Input Offset: 250µV
• Current - Supply: 3.5mA
• Current - Output / Channel: 25mA
• Voltage - Supply, Single/dual (±): ±4.5 V ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Op Amp Type: Precision
• No. Of Amplifiers: 1
• Bandwidth: 13MHz
• Supply Voltage Range: ± 4.5V To ± 18V
• Amplifier Case Style: SOIC
• No. Of Pins: 8
• Common Mode Rejection Ratio: 88
• Current, Input Bias: 30 pA
• Current, Input Offset: 10 pA
• Current, Output: 25 mA
• Harmonic Distortion: 0.0003 %
• Impedance, Thermal: 42 °C/W
• Package Type: SOIC-8
• Power Dissipation: 500 mW
• Resistance, Input: 3×10^12 Ohms
• Temperature, Operating, Range: 0 to +70 °C
• Voltage, Input: ±20 V (Differential), -11.5 to +14.5 V (Common-Mode)
• Voltage, Noise: 45 nV/sqrt Hz
• Voltage, Offset: 0.25 mV
• Voltage, Output, High: +13.9 V
• Voltage, Output, Low: -13.3 V
• Voltage, Supply: ±15 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Gain Bandwidth Product: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

AD744
In either case, the capacitance C
a one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp’s
output. If the value of C
racy, Equation 2 can be used to choose the correct value for
a small capacitor, C
the value of C
As an aid to the designer, the optimum value of C
cific amplifier connection can be determined from the graph of
Figure 41. This graph has been produced for the case where the
AD744 is connected as in Figures 39 and 40 with a practical
minimum value for C
The approximate value of C
application by solving Equation 2. For example, the AD565/
AD744 circuit of Figure 34 constrains all the variables of Equa-
tion 2 (G
Therefore, under these conditions, C
0.370 (9.40)
0.335 (8.50)
0.165
(4.19
0.335 (8.50)
0.305 (7.75)
0.125 (3.18)
N
0.04 (1.0) MAX
0.05 (1.27) MAX
= 3.25, R = 10 kΩ, F
0.25)
0.01
(7.87)
INSULATION
PIN 1
0.31
MIN
0.018
(0.46
0.185 (4.70)
0.165 (4.19)
X
is not known, C
8
0.10 (2.54)
0.39 (9.91)
1
0.003
0.08)
L
MAX
TYP
STRAY
Mini-DIP (N) Package
, which will optimize amplifier response. If
TO-99 (H) Package
X
(0.84)
0.033
NOM
can be estimated with reasonable accu-
5
4
REFERENCE PLANE
0.5 (12.70)
SEATING PLANE
of 2 pF and a total C
8 LEADS
0.019 (0.48)
0.016 (0.41)
L
MIN
0.035
(0.89
(6.35)
0.25
SEATING
PLANE
can be determined for almost any
O
L
X
= 13 MHz, and C
(4.57
should be a variable capacitor.
0.25)
0.18
0.01
causes the system to go from
DIA
L
= 10.5 pF.
0.03
0.76)
EQUALLY
SPACED
0.034 (0.86)
0.028 (0.71)
0-15
45°
0.30 (7.62)
X
REF
1
value of 7.5 pF.
BOTTOM VIEW
2
L
8
0.011
X
(0.28
Dimensions shown in inches and (mm).
0.2 (5.1) TYP
for one spe-
= 32.5 pF)
OUTLINE DIMENSIONS
3
7
0.020 (0.51)
0.045 (1.1)
0.003
0.08)
4
6
5
(0.203
0.008
0.154
(3.91
0.20 (5.08)
0.200 (5.08)
0.125 (3.18)
35
30
25
20
15
10
5
0
100
SEATING
PIN 1
PIN 1
PLANE
MAX
IN THIS REGION
C
G
0.004
0.075)
0.004
0.10)
LEAD
N
0.005 (0.13)
0.023 (0.58)
0.014 (0.36)
= 1 TO
MIN
0.405 (10.29) MAX
Small Outline (SO-8) Package
= 0pF
0.193
(4.90
0.1 (2.54) BSC
0.050 (1.27)
8
1
8
1
BSC
0.017
(0.42
Cerdip (Q) Package
0.008
0.10)
0.07 (1.78)
0.03 (0.76)
0.055 (1.35)
VALUE OF RESISTOR –
5
4
G
1k
MAX
0.003
0.07)
N
5
4
0.236
(6.00
= 1.5
0.098
(2.49
0.310 (7.87)
0.220 (5.59)
0.015 (0.38)
G
0.06 (1.52)
G
N
N
G
SEATING
PLANE
= 1
= 2
N
0.012
0.20)
0.15
(3.81)
MIN
0.006
0.23)
= 3
(0.269
0.011
10k
15°
0°
0.002
0.03)
0.32 (8.13)
0.29 (7.37)
0.033
(0.83
0.015 (0.38)
0.008 (0.20)
0.017
0.43)
100k