LT1920CS8 Linear Technology, LT1920CS8 Datasheet - Page 8

• Manufacturer Part Number: LT1920CS8
• Description: IC PREC INSTRUMNTATION AMP 8SOIC
• Manufacturer: Linear Technology

Specifications of LT1920CS8

• Amplifier Type: Instrumentation
• Number Of Circuits: 1
• Slew Rate: 1.2 V/µs
• Gain Bandwidth Product: 1MHz
• Current - Input Bias: 500pA
• Voltage - Input Offset: 30µV
• Current - Supply: 900µA
• Current - Output / Channel: 27mA
• Voltage - Supply, Single/dual (±): 4.6 V ~ 36 V, ±2.3 V ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• -3db Bandwidth: -

BLOCK
LT1920
THEORY OF OPERATIO
The LT1920 is a modified version of the three op amp
instrumentation amplifier. Laser trimming and monolithic
construction allow tight matching and tracking of circuit
parameters over the specified temperature range. Refer to
the block diagram (Figure 1) to understand the following
circuit description. The collector currents in Q1 and Q2 are
trimmed to minimize offset voltage drift, thus assuring a
high level of performance. R1 and R2 are trimmed to an
absolute value of 24.7k to assure that the gain can be set
accurately (0.3% at G = 100) with only one external
resistor R
determines the transconductance of the preamp stage. As
R
ductance of the input preamp stage increases to that of the
input transistors Q1 and Q2. This increases the open-loop
gain when the programmed gain is increased, reducing
the input referred gain related errors and noise. The input
voltage noise at gains greater than 50 is determined only
by Q1 and Q2. At lower gains the noise of the difference
amplifier and preamp gain setting resistors increase the
noise. The gain bandwidth product is determined by C1,
C2 and the preamp transconductance which increases
8
G
is reduced for larger programmed gains, the transcon-
G
. The value of R
DIAGRAM
–IN
+IN
R
R
G
G
2
1
8
3
V
V
–
–
400
400
W
R3
R4
G
V
V
+
+
in parallel with R1 (R2)
Q1
Q2
U
PREAMP STAGE
VB
VB
Figure 1. Block Diagram
+
–
+
–
24.7k
24.7k
R1
R2
A1
A2
C1
C2
with programmed gain. Therefore, the bandwidth does not
drop proportional to gain.
The input transistors Q1 and Q2 offer excellent matching,
which is inherent in NPN bipolar transistors, as well as
picoampere input bias current due to superbeta process-
ing. The collector currents in Q1 and Q2 are held constant
due to the feedback through the Q1-A1-R1 loop and
Q2-A2-R2 loop which in turn impresses the differential
input voltage across the external gain set resistor R
Since the current that flows through R
R1 and R2, the ratios provide a gained-up differential volt-
age, G = (R1 + R2)/R
A3. The common mode voltage is removed by A3, result-
ing in a single-ended output voltage referenced to the
voltage on the REF pin. The resulting gain equation is:
where:
solving for the gain set resistor gives:
V
G = (49.4k / R
R
OUT
G
= 49.4k /(G – 1)
10k
10k
R5
R7
– V
DIFFERENCE AMPLIFIER STAGE
REF
–
+
= G(V
A3
G
10k
10k
R6
R8
G
) + 1
, to the unity-gain difference amplifier
IN
+
– V
V
V
–
–
IN
–
)
6
5
7
4 V
1920 F01
OUTPUT
REF
V
+
–
G
also flows through
G
.