MCP6232-E/SN Microchip Technology, MCP6232-E/SN Datasheet - Page 8

• Manufacturer Part Number: MCP6232-E/SN
• Description: IC OPAMP 1.8V DUAL R-R 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP6232-E/SN

• Slew Rate: 0.15 V/µs
• Package / Case: 8-SOIC (3.9mm Width)
• Amplifier Type: General Purpose
• Number Of Circuits: 2
• Output Type: Rail-to-Rail
• Gain Bandwidth Product: 300kHz
• Current - Input Bias: 1pA
• Voltage - Input Offset: 5000µV
• Current - Supply: 20µA
• Current - Output / Channel: 23mA
• Voltage - Supply, Single/dual (±): 1.8 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Channels: 2
• Common Mode Rejection Ratio (min): 61 dB
• Input Offset Voltage: 5 mV
• Input Bias Current (max): 1 pA
• Operating Supply Voltage: 3 V, 5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Shutdown: No
• Supply Voltage (max): 6 V
• Supply Voltage (min): 1.8 V
• Technology: CMOS
• Voltage Gain Db: 110 dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP6231/2
FIGURE 3-4:
for Capactive Loads.
After selecting R
resulting frequency response peaking and step
response overshoot. Evaluation on the bench and
simulations with the MCP6231/2 SPICE macro model
are very helpful. Modify R
is reasonable.
3.4
With this op amp, the power supply pin (V
single-supply) should have a local bypass capacitor
(i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-
frequency performance. It also needs a bulk capacitor
(i.e., 1 µF or larger) within 100 mm to provide large,
slow currents. This bulk capacitor can be shared with
other parts.
3.5
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 10
cause 5 pA, if current-to-flow. This is greater than the
MCP6231/2 family’s bias current at 25°C (1 pA, typ).
DS21881B-page 8
10k
100
1k
10p
1.E+04
1.E+03
1.E+02
1.E+01
Supply Bypass
PCB Surface Leakage
Normalized Load Capacitance; C
ISO
100p
for your circuit, double-check the
1.E+02
Recommended R
ISO
12
G
G
G
’s value until the response
N
N
N
= 1 V/V
= 2 V/V
. A 5V difference would
4 V/V
1n
1.E+03
L
/G
ISO
N
(F)
Values
DD
10n
1.E+04
for
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 3-5.
FIGURE 3-5:
for Inverting Gain.
1.
2.
Non-inverting Gain and Unity-Gain Buffer:
a.
b.
Inverting and transimpedance gain amplifiers
(convert current to voltage, such as photo
detectors):
a.
b.
Connect the non-inverting pin (V
input with a wire that does not touch the
PCB surface.
Connect the guard ring to the inverting input
pin (V
common mode input voltage.
Connect the guard ring to the non-inverting
input pin (V
to the same reference voltage as the op
amp (e.g., V
Connect the inverting pin (V
with a wire that does not touch the PCB
surface.
IN
–). This biases the guard ring to the
V
IN
IN
DD
Guard Ring
+). This biases the guard ring
Example Guard Ring Layout
–
 2004 Microchip Technology Inc.
/2 or ground).
V
IN
+
IN
–) to the input
IN
V
SS
+) to the