MCP6232-E/SN Microchip Technology, MCP6232-E/SN Datasheet - Page 7

• Manufacturer Part Number: MCP6232-E/SN
• Description: IC OPAMP 1.8V DUAL R-R 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP6232-E/SN

• Slew Rate: 0.15 V/µs
• Package / Case: 8-SOIC (3.9mm Width)
• Amplifier Type: General Purpose
• Number Of Circuits: 2
• Output Type: Rail-to-Rail
• Gain Bandwidth Product: 300kHz
• Current - Input Bias: 1pA
• Voltage - Input Offset: 5000µV
• Current - Supply: 20µA
• Current - Output / Channel: 23mA
• Voltage - Supply, Single/dual (±): 1.8 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Channels: 2
• Common Mode Rejection Ratio (min): 61 dB
• Input Offset Voltage: 5 mV
• Input Bias Current (max): 1 pA
• Operating Supply Voltage: 3 V, 5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Shutdown: No
• Supply Voltage (max): 6 V
• Supply Voltage (min): 1.8 V
• Technology: CMOS
• Voltage Gain Db: 110 dB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.0
The MCP6231/2 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process and
is specifically designed for low-cost, low-power and
general-purpose applications. The low supply voltage,
low quiescent current and wide bandwidth makes the
MCP6231/2 ideal for battery-powered applications.
3.1
The MCP6231/2 op amps are designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 3-1 shows the input voltage exceeding
the supply voltage without any phase reversal.
FIGURE 3-1:
Phase Reversal.
The input stage of the MCP6231/2 op amps use two
differential input stages in parallel. One operates at low
common mode input voltage (V
high V
V
The
V
proper operation.
Input voltages that exceed the input voltage range
(V
excessive current to flow into or out of the input pins.
Current beyond ±2 mA can cause reliability problems.
Applications that exceed this rating must be externally
limited with a resistor, as shown in Figure 3-2.
 2004 Microchip Technology Inc.
CM
CM
SS
up to 300 mV above V
= V
– 0.3V to V
-1
6
5
4
3
2
1
0
CM
input
0.E+00
SS
APPLICATION INFORMATION
Rail-to-Rail Input
. With this topology, the device operates with
– 300 mV and V
1.E+00
offset
2.E+00
V
OUT
DD
3.E+00
+ 0.3V at 25°C) can cause
The MCP6231/2 Show No
V
Time (1 ms/div)
voltage
IN
4.E+00
DD
5.E+00
DD
and 300 mV below V
CM
+ 300 mV to ensure
6.E+00
is
) and the other at
7.E+00
measured
V
G = +2 V/V
8.E+00
DD
= 5.0V
9.E+00
1.E+01
SS
at
.
FIGURE 3-2:
Resistor (R
3.2
The output voltage range of the MCP6231/2 op amps
is V
R
Refer to Figure 2-14 for more information.
3.3
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, but all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (R
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. It does not,
however, improve the bandwidth.
FIGURE 3-3:
stabilizes large capacitive loads.
Figure 3-4 gives recommended R
different capacitive loads and gains. The x-axis is the
normalized load capacitance (C
circuit’s noise gain. For non-inverting gains, G
gain are equal. For inverting gains, G
(e.g., –1 V/V gives G
L
V
= 10 k
DD
IN
V
IN
– 35 mV (min.) and V
Rail-to-Rail Output
Capacitive Loads
R
R
IN
IN
is connected to V
IN
+
–
MCP623X
).
------------------------------------------------------------------------------ -
R
V
--------------------------------------------------------------------------- -
Maximum expected V
IN
SS
–
N
Minimum expected V
Input Current-Limiting
Output resistor, R
= +2 V/V).
ISO
–
+
MCP623X
MCP6231/2
2 mA
2 mA
in Figure 3-3) improves the
SS
R
DD
L
+ 35 mV (max.) when
ISO
/G
/2 and V
C
N
IN
), where G
L
DS21881B-page 7
ISO
–
N
V
is 1 + |Gain|
IN
DD
ISO
DD
values for
N
V
V
OUT
= 5.5V.
N
and the
OUT
is the