MCP6V01-E/SN Microchip Technology, MCP6V01-E/SN Datasheet - Page 24

• Manufacturer Part Number: MCP6V01-E/SN
• Description: IC OPAMP AUTO-ZERO SNGL 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP6V01-E/SN

• Slew Rate: 0.5 V/µs
• Package / Case: 8-SOIC (3.9mm Width)
• Amplifier Type: Chopper (Zero-Drift)
• Number Of Circuits: 1
• Output Type: Rail-to-Rail
• Gain Bandwidth Product: 1.3MHz
• Current - Input Bias: 1pA
• Voltage - Input Offset: 2µV
• Current - Supply: 300µA
• Current - Output / Channel: 22mA
• Voltage - Supply, Single/dual (±): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Channels: 1
• Common Mode Rejection Ratio (min): 130 dB
• Input Offset Voltage: 0.002 mV
• Input Bias Current (max): 1 pA
• Operating Supply Voltage: 3 V, 5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Shutdown: No
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Technology: CMOS
• Voltage Gain Db: 156 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCP6V01DM-VOS - DEMO BOARD FOR MCP6V01MCP6V01RD-TCPL - REF DESIGN THERMCPL FOR MCP6V01
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP6V01/2/3
4.3
4.3.1
Table 1-1
ture coefficients (TC
The input offset voltage, at any temperature in the
specified range, can be calculated as follows:
EQUATION 4-1:
4.3.2
Figure
of the reciprocals (in units of µV/V) of CMRR, PSRR
and A
input offset voltage (V
mode input voltage (V
and output voltage (V
The 1/A
the measurements are dominated by the op amp’s
input noise. The negative values shown represent
noise, not unstable behavior. We validate the op amps’
stability by making multiple measurements of V
instability would manifest itself as a greater unex-
plained variability in V
4.3.3
The
components; switching glitches that dominate at room
temperature and below, and input ESD diode leakage
currents that dominate at +85°C and above.
Make the resistances seen by the inputs small and
equal. This minimizes the output offset caused by the
input bias currents.
The inputs should see a resistance on the order of 10Ω
to 1 kΩ at high frequencies (i.e., above 1 MHz). This
helps minimize the impact of switching glitches, which
are very fast, on overall performance. In some cases, it
may be necessary to add resistors in series with the
inputs to achieve this improvement in performance.
DS22058C-page 24
Where:
V
OS
OL
input
2-9,
V
(T
TC
TC
OL
, respectively. They represent the change in
ΔT
Application Tips
OS
V
A
gives both the linear and quadratic tempera-
1
2
)
histogram is centered near 0 µV/V because
OS
Figure 2-10
INPUT OFFSET VOLTAGE OVER
TEMPERATURE
DC GAIN PLOTS
SOURCE RESISTANCES
(
bias
T
A
=
=
=
=
=
)
=
1
currents
V
OUT
OS
and TC
CM
T
input offset voltage at T
input offset voltage at +25°C
linear temperature coefficient
quadratic temperature
coefficient
OS
OS
and
A
), power supply voltage (V
or as the railing of the output.
).
– 25°C
) with a change in common
+
TC
Figure 2-11
2
) of input offset voltage.
1
have
ΔT
+
TC
two
are histograms
2
ΔT
2
significant
A
DD
OS
)
;
4.3.4
The capacitances seen by the two inputs should be
small and matched. The internal switches connected to
the inputs dump charges on these capacitors; an offset
can be created if the capacitances do not match.
4.3.5
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. These auto-zeroed op amps have a different
output impedance than most op amps, due to their
unique topology.
When driving a capacitive load with these op amps, a
series resistor at the output (R
improves the feedback loop’s phase margin (stability)
by making the output load resistive at higher frequen-
cies. The bandwidth will be generally lower than the
bandwidth with no capacitive load.
FIGURE 4-6:
Stabilizes Capacitive Loads.
Figure 4-7
different capacitive loads and is independent of the
gain.
FIGURE 4-7:
for Capacitive Loads.
10000
1000
100
10k
100
10
1k
10
1.E-12
1p
SOURCE CAPACITANCE
CAPACITIVE LOADS
gives recommended R
1.E-11
MCP6V0X
10p
G
G
N
N
Output Resistor, R
Recommended R
1.E-10
100p
= 5
= 10
© 2008 Microchip Technology Inc.
G
C
N
L
< 2
(F)
1.E-09
1n
R
ISO
ISO
C
L
ISO
1.E-08
10n
in
ISO
ISO
values for
Figure
V
OUT
values
,
1.E-07
100n
4-6)