LF347N/NOPB National Semiconductor, LF347N/NOPB Datasheet - Page 9

• Manufacturer Part Number: LF347N/NOPB
• Description: IC OP AMP QUAD JFET WIDE 14-DIP
• Manufacturer: National Semiconductor
• Series: BI-FET II™r

Specifications of LF347N/NOPB

• Amplifier Type: J-FET
• Number Of Circuits: 4
• Slew Rate: 13 V/µs
• Gain Bandwidth Product: 4MHz
• Current - Input Bias: 50pA
• Voltage - Input Offset: 5000µV
• Current - Supply: 7.2mA
• Voltage - Supply, Single/dual (±): 8 V ~ 36 V, ±4 V ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 14-DIP (0.300", 7.62mm)
• Bandwidth: 4 MHz
• Channel Separation: -120
• Common Mode Rejection Ratio: 100
• Current, Input Bias: 50 pA
• Current, Input Offset: 25 pA
• Current, Output: 31 mA
• Current, Supply: 7.2 mA
• Harmonic Distortion: 0.02 %
• Impedance, Thermal: 75 °C/W
• Number Of Amplifiers: Quad
• Package Type: MDIP-14
• Power Dissipation: 1000 mW
• Resistance, Input: 10^12 Ohms
• Temperature, Operating, Range: 0 to +70 °C
• Voltage, Gain: 100 V/mV
• Voltage, Input: 8 to 36 V
• Voltage, Noise: 20 nV/sqrt Hz
• Voltage, Offset: 5 mV
• Voltage, Output, High: 13.5 V
• Voltage, Output, Low: -13.5 V
• Voltage, Supply: ±15 V
• Number Of Channels: 4
• Voltage Gain Db: 100 dB
• Common Mode Rejection Ratio (min): 70 dB
• Input Voltage Range (max): 36 V
• Input Voltage Range (min): 8 V
• Input Offset Voltage: 10 mV at +/- 15 V
• Supply Current: 11 mA at +/- 15 V
• Maximum Power Dissipation: 1000 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Maximum Dual Supply Voltage: +/- 18 V
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Current - Output / Channel: -
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device
• Other names: *LF347N; *LF347N/NOPB; LF347; LF347NNS

Application Hints
Exceeding the positive common-mode limit on a single input
will not change the phase of the output; however, if both
inputs exceed the limit, the output of the amplifier will be
forced to a high state.
The amplifiers will operate with a common-mode input volt-
age equal to the positive supply; however, the gain band-
width and slew rate may be decreased in this condition.
When the negative common-mode voltage swings to within
3V of the negative supply, an increase in input offset voltage
may occur.
Each amplifier is individually biased by a zener reference
which allows normal circuit operation on
plies. Supply voltages less than these may result in lower
gain bandwidth and slew rate.
The LF147 will drive a 2 kΩ load resistance to
full temperature range. If the amplifier is forced to drive
heavier load currents, however, an increase in input offset
voltage may occur on the negative voltage swing and finally
reach an active current limit on both positive and negative
swings.
Precautions should be taken to ensure that the power supply
for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in a
(Continued)
±
4.5V power sup-
±
10V over the
9
socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal
conductors and result in a destroyed unit.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in order
to ensure stability. For example, resistors from the output to
an input should be placed with the body close to the input to
minimize “pick-up” and maximize the frequency of the feed-
back pole by minimizing the capacitance from the input to
ground.
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) to AC
ground set the frequency of the pole. In many instances the
frequency of this pole is much greater than the expected 3
dB frequency of the closed loop gain and consequently there
is negligible effect on stability margin. However, if the feed-
back pole is less than approximately 6 times the expected 3
dB frequency a lead capacitor should be placed from the
output to the input of the op amp. The value of the added
capacitor should be such that the RC time constant of this
capacitor and the resistance it parallels is greater than or
equal to the original feedback pole time constant.
Detailed Schematic
00564709
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