LF442CN/NOPB National Semiconductor, LF442CN/NOPB Datasheet - Page 9

• Manufacturer Part Number: LF442CN/NOPB
• Description: IC OP AMP DUAL LO PWR JFET 8-DIP
• Manufacturer: National Semiconductor
• Series: BI-FET II™r

Specifications of LF442CN/NOPB

• Amplifier Type: J-FET
• Number Of Circuits: 2
• Slew Rate: 1 V/µs
• Gain Bandwidth Product: 1MHz
• Current - Input Bias: 10pA
• Voltage - Input Offset: 1000µV
• Current - Supply: 400µA
• Voltage - Supply, Single/dual (±): 10 V ~ 36 V, ±5 V ~ 18 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Bandwidth: 1 MHz
• Channel Separation: -120
• Common Mode Rejection Ratio: 95
• Current, Input Bias: 10 pA
• Current, Input Offset: 5 pA
• Current, Output: 6.8 mA
• Current, Supply: 400 μA
• Impedance, Thermal: 152 °C/W
• Number Of Amplifiers: Dual
• Package Type: MDIP-8
• Resistance, Input: 10^12 Ohms
• Temperature, Operating, Range: 0 to +70 °C
• Voltage, Gain: 200 V/mV
• Voltage, Input: 6 to 44 V
• Voltage, Noise: 35 nV/sqrt Hz
• Voltage, Offset: 1 mV
• Voltage, Output, High: 13 V
• Voltage, Output, Low: -13 V
• Voltage, Supply: ±15 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Current - Output / Channel: -
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device
• Other names: *LF442CN; *LF442CN/NOPB; LF442; LF442CN

Application Hints
This device is a dual low power op amp with internally
trimmed input offset voltages and JFET input devices (BI-
FET II). These JFETs have large reverse breakdown volt-
ages from gate to source and drain eliminating the need for
clamps across the inputs. Therefore, large differential input
voltages can easily be accommodated without a large in-
crease in input current. The maximum differential input volt-
age is independent of the supply voltages. However, neither
of the input voltages should be allowed to exceed the nega-
tive supply as this will cause large currents to flow which can
result in a destroyed unit.
Exceeding the negative common-mode limit on either input
will force the output to a high state, potentially causing a
reversal of phase to the output. Exceeding the negative
common-mode limit on both inputs will force the amplifier
output to a high state. In neither case does a latch occur
since raising the input back within the common-mode range
again puts the input stage and thus the amplifier in a normal
operating mode.
Exceeding the positive common-mode limit on a single input
will not change the phase of the output; however, if both
inputs exceed the limit, the output of the amplifier will be
forced to a high state.
The amplifiers will operate with a common-mode input volt-
age equal to the positive supply; however, the gain band-
width and slew rate may be decreased in this condition.
When the negative common-mode voltage swings to within
3V of the negative supply, an increase in input offset voltage
may occur.
Each amplifier is individually biased to allow normal circuit
operation with power supplies of
than these may degrade the common-mode rejection and
restrict the output voltage swing.
Typical Applications
Runs from 9v batteries (
Fully settable gain and time constant
Battery powered supply allows direct plug-in interface to strip chart recorder without common-mode problems
±
9V supplies)
±
3.0V. Supply voltages less
Battery Powered Strip Chart Preamplifier
9
The amplifiers will drive a 10 kΩ load resistance to
over the full temperature range.
Precautions should be taken to ensure that the power supply
for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in a
socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal
conductors and result in a destroyed unit.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in order
to ensure stability. For example, resistors from the output to
an input should be placed with the body close to the input to
minimize “pick-up” and maximize the frequency of the feed-
back pole by minimizing the capacitance from the input to
ground.
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) to AC
ground set the frequency of the pole. In many instances the
frequency of this pole is much greater than the expected 3
dB frequency of the closed loop gain and consequenty there
is negligible effect on stability margin. However, if the feed-
back pole is less than approximately 6 times the expected 3
dB frequency a lead capacitor should be placed from the
output to the input of the op amp. The value of the added
capacitor should be such that the RC time constant of this
capacitor and the resistance it parallels is greater than or
equal to the original feedback pole time constant.
00915511
www.national.com
±
10V