AD8221BR Analog Devices Inc, AD8221BR Datasheet - Page 18

IC AMP INST PREC LN 18MA 8SOIC

AD8221BR

Manufacturer Part Number
AD8221BR
Description
IC AMP INST PREC LN 18MA 8SOIC
Manufacturer
Analog Devices Inc
Type
Instrumentation Ampr
Datasheets

Specifications of AD8221BR

Rohs Status
RoHS non-compliant
Design Resources
Low Cost, High Voltage, Programmable Gain Instrumentation Amplifier Using AD5292 and AD8221 (CN0114) Low Cost Programmable Gain Instrumentation Amplifier Circuit Using ADG1611 and AD620 (CN0146)
Amplifier Type
Instrumentation
Number Of Circuits
1
Slew Rate
2 V/µs
-3db Bandwidth
825kHz
Current - Input Bias
200pA
Voltage - Input Offset
25µV
Current - Supply
900µA
Current - Output / Channel
18mA
Voltage - Supply, Single/dual (±)
4.6 V ~ 36 V, ±2.3 V ~ 18 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Number Of Channels
1
Number Of Elements
1
Power Supply Requirement
Dual
Common Mode Rejection Ratio
140dB
Voltage Gain Db
60dB
Input Resistance
100000@±15VMohm
Input Offset Voltage
0.025@±15VmV
Input Bias Current
0.0004@±15VnA
Single Supply Voltage (typ)
Not RequiredV
Power Supply Rejection Ratio
140dB
Power Dissipation
200mW
Rail/rail I/o Type
No
Single Supply Voltage (min)
Not RequiredV
Single Supply Voltage (max)
Not RequiredV
Dual Supply Voltage (min)
±2.3V
Dual Supply Voltage (max)
±18V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
8
Package Type
SOIC N
No. Of Amplifiers
1
Gain Db Min
1dB
Bandwidth
825kHz
Amplifier Output
Single Ended
Cmrr
140dB
Supply Voltage Range
± 2.3V To ± 18V
Rohs Compliant
No
Output Type
-
Gain Bandwidth Product
-
Lead Free Status / RoHS Status
Not Compliant

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AD8221
GAIN SELECTION
Placing a resistor across the R
AD8221, which can be calculated by referring to Table 6 or
by using the gain equation.
Table 6. Gains Achieved Using 1% Resistors
1% Standard Table Value of R
49.9 k
12.4 k
5.49 k
2.61 k
1.00 k
499
249
100
49.9
The AD8221 defaults to G = 1 when no gain resistor is used.
Gain accuracy is determined by the absolute tolerance of R
The TC of the external gain resistor increases the gain drift of
the instrumentation amplifier. Gain error and gain drift are kept
to a minimum when the gain resistor is not used.
LAYOUT
Careful board layout maximizes system performance. Traces
from the gain setting resistor to the R
short as possible to minimize parasitic inductance. To ensure
the most accurate output, the trace from the REF pin should
either be connected to the local ground of the AD8221, as shown
in Figure 47, or connected to a voltage that is referenced to the
local ground of the AD8221.
Common-Mode Rejection
One benefit of the high CMRR over frequency of the AD8221 is
that it has greater immunity to disturbances, such as line noise
and its associated harmonics, than do typical instrumentation
amplifiers. Typically, these amplifiers have CMRR fall-off at
200 Hz; common-mode filters are often used to compensate for
this shortcoming. The AD8221 is able to reject CMRR over a
greater frequency range, reducing the need for filtering.
A well implemented layout helps to maintain the high CMRR
over frequency of the AD8221. Input source impedance and
capacitance should be closely matched. In addition, source
resistance and capacitance should be placed as close to the
inputs as permissible.
R
G
=
49
G
4 .
1
G
G
terminals set the gain of
(Ω)
G
pins should be kept as
Calculated Gain
1.990
4.984
9.998
19.93
50.40
100.0
199.4
495.0
991.0
G
.
Rev. C | Page 18 of 24
Grounding
The output voltage of the AD8221 is developed with respect to
the potential on the reference terminal. Care should be taken to
tie REF to the appropriate local ground.
In mixed-signal environments, low level analog signals need to
be isolated from the noisy digital environment. Many ADCs
have separate analog and digital ground pins. Although it is
convenient to tie both grounds to a single ground plane, the
current traveling through the ground wires and PC board may
cause hundreds of millivolts of error. Therefore, separate analog
and digital ground returns should be used to minimize the
current flow from sensitive points to the system ground. An
example layout is shown in Figure 45 and Figure 46.
Figure 46. Bottom Layer of the AD8221-EVAL
Figure 45. Top Layer of the AD8221-EVAL

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