AD629ANZ Analog Devices Inc, AD629ANZ Datasheet - Page 9

• Manufacturer Part Number: AD629ANZ
• Description: IC AMP DIFF 25MA LDRIFT 8DIP
• Manufacturer: Analog Devices Inc
• Type: Differential Amplifierr

Specifications of AD629ANZ

• Design Resources: Measuring -48 V High-Side Current Using AD629, AD8603, AD780, and AD7453 (CN0100)
• Amplifier Type: Differential
• Number Of Circuits: 1
• Slew Rate: 2.1 V/µs
• -3db Bandwidth: 500kHz
• Voltage - Input Offset: 200µV
• Current - Supply: 900µA
• Current - Output / Channel: 25mA
• Voltage - Supply, Single/dual (±): 5 V ~ 36 V, ±2.5 V ~ 18 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• No. Of Amplifiers: 1
• Input Offset Voltage: 1mV
• Gain Db Max: 1dB
• Bandwidth: 500kHz
• Supply Voltage Range: ± 2.5V To ± 18V
• Supply Current: 900µA
• Amplifier Case Style: DIP
• Rohs Compliant: Yes
• Number Of Channels: 1
• Number Of Elements: 1
• Power Supply Requirement: Dual
• Common Mode Rejection Ratio: 77dB
• Voltage Gain Db: 0dB
• Single Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (typ): ±3/±5/±9/±12/±15V
• Power Supply Rejection Ratio: 84dB
• Rail/rail I/o Type: No
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): ±2.5V
• Dual Supply Voltage (max): ±18V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 8
• Package Type: PDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• Gain Bandwidth Product: -
• Current - Input Bias: -
• Lead Free Status / Rohs Status: Compliant

Figure 26. Typical Distribution of Common-Mode Rejection; Package Option N-8
Figure 25. Settling Time to 0.01%, for 0 V to 10 V Output Step; G = −1, R
Figure 27. Typical Distribution of −1 Gain Error; Package Option N-8
350
300
250
200
150
100
400
350
300
250
200
150
100
50
50
–150
–600
+10V
0
0
1mV/DIV
0V
5V/DIV
V
OUTPUT
ERROR
OUT
N = 2180
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
N = 2180
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
–100
–400
COMMON-MODE REJECTION RATIO (ppm)
–200
–50
–1 GAIN ERROR (ppm)
0
0
200
50
1mV = 0.01%
10µs/DIV
100
400
L
= 2 kΩ
150
600
Rev. C | Page 9 of 16
Figure 28. Settling Time to 0.01% for 0 V to −10 V Output Step; G = −1, R
Figure 29. Typical Distribution of Offset Voltage; Package Option N-8
Figure 30. Typical Distribution of +1 Gain Error; Package Option N-8
300
250
200
150
100
400
350
300
250
200
150
100
50
50
–10V
–600
0
0
1mV/DIV
0V
5V/DIV
V
–900
OUT
OUTPUT
ERROR
N = 2180
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
N = 2180
n ≈ 200 PCS. FROM
10 ASSEMBLY LOTS
–400
–600
–200
–300
OFFSET VOLTAGE (µV)
+1 GAIN ERROR (ppm)
0
0
300
200
1mV = 0.01%
10µs/DIV
600
400
AD629
900
L
600
= 2kΩ