SAK-XC161CS-32F20F BB-A Infineon Technologies, SAK-XC161CS-32F20F BB-A Datasheet - Page 6
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SAK-XC161CS-32F20F BB-A
Manufacturer Part Number
SAK-XC161CS-32F20F BB-A
Description
IC MCU 16BIT 256KB TQFP-144-19
Manufacturer
Infineon Technologies
Series
XC16xr
Datasheet
1.SAF-XC161CS-32F20F_BB-A.pdf
(87 pages)
Specifications of SAK-XC161CS-32F20F BB-A
Core Processor
C166SV2
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
PWM, WDT
Number Of I /o
99
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.7 V
Data Converters
A/D 12x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-LFQFP
Data Bus Width
16 bit
Data Ram Size
12 KB
Interface Type
ASC, CAN, IIC, SSC
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
99
Number Of Timers
9
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
For Use With
MCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
KX161CS32F20FBBANT
KX161CS32F20FBBAXT
SAKXC161CS32F20FBBAT
SP000098774
SP000224543
KX161CS32F20FBBAXT
SAKXC161CS32F20FBBAT
SP000098774
SP000224543
16-Bit Single-Chip Microcontroller with C166SV2 Core
XC166 Family
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Data Sheet
High Performance 16-bit CPU with 5-Stage Pipeline
– 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
– 1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
– 1-Cycle Multiply-and-Accumulate (MAC) Instructions
– Enhanced Boolean Bit Manipulation Facilities
– Zero-Cycle Jump Execution
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Fast Context Switching Support with Two Additional Local Register Banks
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 bytes On-Chip Special Function Register Area (C166 Family Compatible)
16-Priority-Level Interrupt System with 73 Sources, Sample-Rate down to 50 ns
8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or
via Prescaler (factors 1:1 … 60:1)
On-Chip Memory Modules
– 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
– 4 Kbytes On-Chip Data SRAM (DSRAM)
– 6 Kbytes On-Chip Program/Data SRAM (PSRAM)
– 256 Kbytes On-Chip Program Memory (Flash Memory)
On-Chip Peripheral Modules
– 12-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and
– Two 16-Channel General Purpose Capture/Compare Units (32 Input/Output Pins)
– Multi-Functional General Purpose Timer Unit with 5 Timers
– Two Synchronous/Asynchronous Serial Channels (USARTs)
– Two High-Speed-Synchronous Serial Channels
– On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects
– IIC Bus Interface (10-bit addressing, 400 kbit/s) with 3 Channels (multiplexed)
– On-Chip Real Time Clock, Driven by Dedicated Oscillator
Idle, Sleep, and Power Down Modes with Flexible Power Management
Programmable Watchdog Timer and Oscillator Watchdog
Conversion Time (down to 2.55 µs or 2.15 µs)
(Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality
Summary of Features
4
V1.2, 2006-08
XC161