SAF-XC167CI-16F20F BB Infineon Technologies, SAF-XC167CI-16F20F BB Datasheet - Page 70

• Manufacturer Part Number: SAF-XC167CI-16F20F BB
• Description: IC MCU 16BIT 128KB TQFP-144-19
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAF-XC167CI-16F20F BB

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 103
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFQFP
• For Use With: B158-H8963-X-X-7600IN - KIT EASY XC167CIMCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: FX167CI16F20FBBNP; FX167CI16F20FBBXP; SAFXC167CI16F20FBB; SP000094528; SP000224688

4.4
4.4.1
The internal operation of the XC167 is controlled by the internal master clock
The master clock signal
different mechanisms. The duration of master clock periods (TCMs) and their variation
(and also the derived external timing) depend on the used mechanism to generate
This influence must be regarded when calculating the timings for the XC167.
Figure 15
Note: The example for PLL operation shown in
The used mechanism to generate the master clock is selected by register PLLCON.
CPU and EBC are clocked with the CPU clock signal
same frequency as the master clock (
two:
Data Sheet
f
CPU
the example for prescaler operation refers to a divider factor of 2:1.
Phase Locked Loop Operation (1:N)
f
f
Direct Clock Drive (1:1)
f
f
Prescaler Operation (N:1)
f
f
OSC
MC
OSC
MC
OSC
MC
=
f
AC Parameters
Definition of Internal Timing
MC
Generation Mechanisms for the Master Clock
/ 2. This factor is selected by bit CPSYS in register SYSCON1.
f
MC
can be generated from the oscillator clock signal
f
CPU
68
=
f
MC
) or can be the master clock divided by
Figure 15
f
CPU
. The CPU clock can have the
refers to a PLL factor of 1:4,
TCM
Electrical Parameters
TCM
TCM
MCT05555
XC167CI-16F
Derivatives
V1.3, 2006-08
f
MC
f
OSC
.
f
MC
via
.