SAF-XC164CS-16F20F BB Infineon Technologies, SAF-XC164CS-16F20F BB Datasheet - Page 31

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SAF-XC164CS-16F20F BB

Manufacturer Part Number
SAF-XC164CS-16F20F BB
Description
IC MCU 16BIT FLASH TQFP-100-16
Manufacturer
Infineon Technologies
Series
XC16xr
Datasheet

Specifications of SAF-XC164CS-16F20F BB

Core Processor
C166SV2
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, SPI, UART/USART
Peripherals
PWM, WDT
Number Of I /o
79
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.7 V
Data Converters
A/D 14x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Packages
PG-TQFP-100
Max Clock Frequency
20.0 MHz
Sram (incl. Cache)
8.0 KByte
Can Nodes
2
A / D Input Lines (incl. Fadc)
14
Program Memory
128.0 KByte
For Use With
B158-H8962-X-X-7600IN - KIT EASY XC164CSMCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
FX164CS16F20FBBNP
FX164CS16F20FBBXT
SAFXC164CS16F20FBB
SP000094305
SP000224550
3.6
The CAPCOM units support generation and control of timing sequences on up to
32 channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered
mode). The CAPCOM units are typically used to handle high speed I/O tasks such as
pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A)
conversion, software timing, or time recording relative to external events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time
bases for each capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, external count
inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/compare
registers relative to external events.
Both of the two capture/compare register arrays contain 16 dual purpose
capture/compare registers, each of which may be individually allocated to either
CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or
compare function.
12 registers of the CAPCOM2 module have each one port pin associated with it which
serves as an input pin for triggering the capture function, or as an output pin to indicate
the occurrence of a compare event.
Table 6
Compare Modes
Mode 0
Mode 1
Mode 2
Mode 3
Double Register
Mode
Single Event Mode
Data Sheet
Capture/Compare Units (CAPCOM1/2)
Compare Modes (CAPCOM1/2)
Function
Interrupt-only compare mode;
several compare interrupts per timer period are possible
Pin toggles on each compare match;
several compare events per timer period are possible
Interrupt-only compare mode;
only one compare interrupt per timer period is generated
Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;
only one compare event per timer period is generated
Two registers operate on one pin;
pin toggles on each compare match;
several compare events per timer period are possible
Generates single edges or pulses;
can be used with any compare mode
29
Functional Description
Derivatives
V2.3, 2006-08
XC164CS

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