SAF-C164CI-L25M CA Infineon Technologies, SAF-C164CI-L25M CA Datasheet - Page 31

• Manufacturer Part Number: SAF-C164CI-L25M CA
• Description: IC MCU 16BIT OTP MQFP-80-1
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C164CI-L25M CA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-SQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: SAFC164CIL25MCAT; SP000014436

C164CI/SI
C164CL/SL
CAN-Module
The integrated CAN-Module handles the completely autonomous transmission and
reception of CAN frames in accordance with the CAN specification V2.0 part B (active),
i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit
identifiers as well as extended frames with 29-bit identifiers.
The module provides Full CAN functionality on up to 15 message objects. Message
object 15 may be configured for Basic CAN functionality. Both modes provide separate
masks for acceptance filtering which allows to accept a number of identifiers in Full CAN
mode and also allows to disregard a number of identifiers in Basic CAN mode. All
message objects can be updated independent from the other objects and are equipped
for the maximum message length of 8 bytes.
The bit timing is derived from the XCLK and is programmable up to a data rate of 1 Mbit/
s. Each CAN-Module uses two pins of Port 4 or Port 8 to interface to an external bus
transceiver. The interface pins are assigned via software.
Note: When the CAN interface is assigned to Port 4, the respective segment address
lines on Port 4 cannot be used. This will limit the external address space.
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be
disabled in the time interval until the EINIT (end of initialization) instruction has been
executed. Thus, the chip’s start-up procedure is always monitored. The software has to
be designed to service the Watchdog Timer before it overflows. If, due to hardware or
software related failures, the software fails to do so, the Watchdog Timer overflows and
generates an internal hardware reset and pulls the RSTOUT pin low in order to allow
external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/
256. The high byte of the Watchdog Timer register can be set to a prespecified reload
value (stored in WDTREL) in order to allow further variation of the monitored time
interval. Each time it is serviced by the application software, the high byte of the
Watchdog Timer is reloaded. Thus, time intervals between 20 µs and 336 ms can be
monitored (@ 25 MHz).
The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz).
Data Sheet
27
V2.0, 2001-05